WILLIAM J BUCKLEY
Broker in Boston, MA
License number
Massachusetts 9046996
Issued Date
Jun 22, 2002
Expiration Date
Dec 29, 2004
Type
Salesperson
Address
Address
Boston, MA 02120
Professional information
Senior Systems Engineer
Position:
Senior Software Engineer at Monster Worldwide
Location:
Greater Boston Area
Industry:
Information Technology and Services
Work:
Monster Worldwide
- Maynard, MA since Jan 2008
-
Senior Software Engineer
European Coaster Club
1995 - 2008
-
North American Editor
MultiPlan
Oct 2006 - Dec 2007
-
Manager, Internet Engineering
PHCS / Private Healthcare Systems
Aug 2000 - Sep 2006
-
Internet Engineer II
Compaq Computer Corp.
Apr 1998 - Aug 2000
-
Technology Consultant
DEC / Digital Equipment Corporation
Sep 1978 - Mar 1998
-
Various Positions
Education:
Worcester Polytechnic Institute 2001 - 2005
BS, Computer Science Boston University 1998 - 1999
Certificate, Client/Server Application Development Berklee College of Music 1981 - 1985
B.S., Audio Engineering
BS, Computer Science Boston University 1998 - 1999
Certificate, Client/Server Application Development Berklee College of Music 1981 - 1985
B.S., Audio Engineering
Skills:
Marketing, Web Application Design, Systems Management, XML, Requirements Analysis, SharePoint, Software Development, SDLC, Oracle, Databases, Integration, SQL, Software Project Management, Team Leadership, Testing, Business Analysis, Microsoft SQL Server, Data Warehousing, Project Management, JavaScript, Troubleshooting, Security, Active Directory, Windows Server, Web Applications
Interests:
Amusement and Theme Parks, Roller Coasters, Motorcycles, Playing Rock Guitar, Equitation, Travel.
Certifications:
IBM Certified Specialist - Unica Campaign V8.5, IBM
Operations Services Professional
Location:
Greater Boston Area
Industry:
Facilities Services
Work:
Oce Business Services
2006 - 2008
-
Project Manager
KPMG, LLP
1996 - 2006
-
Director, Operations Services
Recovering From A Storage Processor Failure Using Write Cache Preservation
US Patent:
7809975, Oct 5, 2010
Filed:
Mar 29, 2007
Appl. No.:
11/729728
Inventors:
David French - Grafton MA, US
Douglas Sullivan - Hopkinton MA, US
William Buckley - Brighton MA, US
Alex Sanville - Boxborough MA, US
Phillip J. Manning - East Geenwich RI, US
Douglas Sullivan - Hopkinton MA, US
William Buckley - Brighton MA, US
Alex Sanville - Boxborough MA, US
Phillip J. Manning - East Geenwich RI, US
Assignee:
EMC Corporation - Hopkinton MA
International Classification:
G06F 11/00
US Classification:
714 3
Abstract:
A computerized system includes two storage processors having respective local write caches configured to mirror each other. When a first storage processor becomes unavailable and mirroring of the local write caches is prevented, the computerized system continues to attend to write operations from an external host in a write-back manner by caching write data from the write operations in the local write cache of the second storage processor. In response to a failure of the second storage processor, the computerized system preserves the write data within the local write cache of the second storage processor. Then, upon recovery of the second storage processor from the failure, the computerized system continues to attend to further write operations from the external host in the write-back manner by caching additional write data in the local write cache of the second storage processor while the first storage processor remains unavailable.
Managing Communications Paths
US Patent:
2007023, Oct 4, 2007
Filed:
Mar 30, 2006
Appl. No.:
11/393230
Inventors:
Steven Sardella - Hudson MA, US
Douglas Sullivan - Hopkinton MA, US
William Buckley - Brighton MA, US
Christopher Towns - Framingham MA, US
Douglas Sullivan - Hopkinton MA, US
William Buckley - Brighton MA, US
Christopher Towns - Framingham MA, US
International Classification:
G06F 11/00
US Classification:
714023000
Abstract:
Communications paths are managed. An error is detected on a first storage processor. It is determined that the error resulted from a peer-to-peer communication from a second storage processor. The error on the first storage processor is handled by taking action short of causing the first storage processor to reset.