DR. WILLIAM H. THOMPSON, M.D.
Osteopathic Medicine at Gala St, Meridian, ID

License number
Idaho M-8604
Category
Osteopathic Medicine
Type
Critical Care Medicine
License number
Idaho M-8604
Category
Osteopathic Medicine
Type
Pulmonary Disease
License number
Idaho M8604
Category
Osteopathic Medicine
Type
Sleep Medicine
Address
Address 2
2347 E Gala St, Meridian, ID 83642
190 E Bannock St, Boise, ID 83712
Phone
(208) 323-3767
(208) 381-2222

Professional information

William Herbert Thompson Photo 1

William Herbert Thompson, Meridian ID

Specialties:
Internal Medicine, Pulmonary Disease, Critical Care Medicine, Sleep Medicine, Critical Care Medicine
Work:
St Luke's Idaho Cardiology
2347 E Gala St, Meridian, ID 83642 St Luke's Sleep Medicine Institute
190 E Bannock St, Boise, ID 83712 St Luke's Clinic Pulmonology
2051 E Summersweet Dr, Boise, ID 83716 St Luke's McCall Memorial Hospital
200 Forest St, McCall, ID 83638 Pulmonary Disease/Sleep Disorders
52347 E Gala St, Meridian, ID 83642 Saint Luke's Meridian Medical Center
520 S Eagle Rd, Meridian, ID 83642 St Lukes Idaho Pulmonary Associates
125 E Idaho St, Boise, ID 83712
Education:
Johns Hopkins University (1988) *


William Thompson Photo 2

William Thompson - Meridian, ID

Work:
AutoZone
Store Manager, Store 1185
Advance Auto Parts - Richmond, KY
General Manager, Store
Wal-Mart - Lexington, KY
Asset Protection Coordinator, Store
Wal-Mart - Lexington, KY
TLE Service Manager/Automotive Department Manager
Wal-Mart Inc
Sales Associate/Customer Relations
Education:
Eastern Kentucky University - Richmond, KY
Bachelor of Arts in General Studies


William Thompson Photo 3

Latch-Up Prevention For Memory Cells

US Patent:
6376297, Apr 23, 2002
Filed:
Aug 5, 1999
Appl. No.:
09/368710
Inventors:
John D. Porter - Meridian ID
William N. Thompson - Meridian ID
Assignee:
Micron Technology, Inc. - Dayton OH
International Classification:
H01L 218234
US Classification:
438238, 438199, 438200, 438202
Abstract:
An SRAM memory cell is provided having a pair of cross-coupled CMOS inverters. The sources of the pull-up transistors forming each of the CMOS inverters are coupled to V through parasitic resistance of the substrate in which each is formed. The source of the p-type pull-up transistor is therefore always at a potential less than or equal to the potential of the N-well such that the emitter-base junction of the parasitic PNP transistor cannot become forward biased and latch-up cannot occur.


William Thompson Photo 4

Method To Find A Value Within A Range Using Weighted Subranges

US Patent:
6384714, May 7, 2002
Filed:
Aug 6, 2001
Appl. No.:
09/922983
Inventors:
William N. Thompson - Meridian ID
John D. Porter - Meridian ID
Larren Gene Weber - Caldwell ID
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
G05B 100
US Classification:
3401462, 377 26, 377 39, 377 51
Abstract:
A method of finding an unknown value from within a range of values is disclosed that divides the range into weighted subranges and then, beginning with an arbitrary search value within the range, performs a number of simple comparisons to determine the value for each subrange that will result in a match with the target value. This method can also detect those cases where the target value lies outside the range. In one embodiment, the method of finding an unknown value within a range of values is applied to impedance matching. In this embodiment, the output impedance of a pin on an integrated circuit is automatically matched to the impedance of the load connected to it. The output driver has a controllable impedance that can be adjusted within a specific range of impedances to match the external load impedance it is to drive.


William Thompson Photo 5

Method To Find A Value Within A Range Using Weighted Subranges

US Patent:
6545561, Apr 8, 2003
Filed:
Aug 14, 2001
Appl. No.:
09/929571
Inventors:
William N. Thompson - Meridian ID
John D. Porter - Meridian ID
Larren Gene Weber - Caldwell ID
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
H03H 1130
US Classification:
333 173, 333 32
Abstract:
A method of finding an unknown value from within a range of values is disclosed that divides the range into weighted subranges and then, beginning with an arbitrary search value within the range, performs a number of simple comparisons to determine the value for each subrange that will result in a match with the target value. This method can also detect those cases where the target value lies outside the range. In one embodiment, the method of finding an unknown value within a range of values is applied to impedance matching. In this embodiment, the output impedance of a pin on an integrated circuit is automatically matched to the impedance of the load connected to it. The output driver has a controllable impedance that can be adjusted within a specific range of impedances to match the external load impedance it is to drive.


William Thompson Photo 6

Method To Find A Value Within A Range Using Weighted Subranges

US Patent:
6275119, Aug 14, 2001
Filed:
Aug 25, 1999
Appl. No.:
9/382525
Inventors:
William N. Thompson - Meridian ID
John D. Porter - Meridian ID
Larren Gene Weber - Caldwell ID
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
H03H 1130, H03H 1128
US Classification:
333 173
Abstract:
A method of finding an unknown value from within a range of values is disclosed that divides the range into weighted subranges and then, beginning with an arbitrary search value within the range, performs a number of simple comparisons to determine the value for each subrange that will result in a match with the target value. This method can also detect those cases where the target value lies outside the range. In one embodiment, the method of finding an unknown value within a range of values is applied to impedance matching. In this embodiment, the output impedance of a pin on an integrated circuit is automatically matched to the impedance of the load connected to it. The output driver has a controllable impedance that can be adjusted within a specific range of impedances to match the external load impedance it is to drive.


William Thompson Photo 7

Method And Apparatus For Accessing One Of A Plurality Of Memory Units Within An Electronic Memory Device

US Patent:
6128244, Oct 3, 2000
Filed:
Jun 4, 1998
Appl. No.:
9/090167
Inventors:
William N. Thompson - Meridian ID
J. David Porter - Meridian ID
Larren G. Weber - Caldwell ID
John Wilford - Boise ID
Tom Pawlowski - Boise ID
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
G11C 800
US Classification:
36523003
Abstract:
The invention provides a memory access system and method of operation particularly useful with electronic storage devices having two or more memory units. Accessing of the memory units occurs one at a time and takes place using shared resources, such as shared row and column decoders. In a preferred embodiment, the invention permits the parallel reading of data from one memory unit of a plurality of memory units during a single system clock cycle using shared resources to perform addressing (e. g. , read or write access) for the memory unit. The same shared resources are then used by any one of the other memory units during a subsequent system clock cycle to perform its own access function. By reading (or writing) data from (or to) one memory unit only during a single system clock cycle, the shared row and column decoders (and their attendant address lines) become available in a subsequent system clock cycle for use by another memory unit.


William Thompson Photo 8

Latching Sense Amplifier Structure With Pre-Amplifier

US Patent:
6088278, Jul 11, 2000
Filed:
Jul 23, 1998
Appl. No.:
9/121145
Inventors:
John D. Porter - Meridian ID
William N. Thompson - Meridian ID
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
G11C 700
US Classification:
365208
Abstract:
An apparatus and method for sensing the logical state stored in a memory cell includes a pre-amplifier and a latching sense amplifier. The pre-amplifier receives differential signals from a memory array, shifts the signals and amplifies the differential sufficiently for input to the latching sense amplifier. The gain realized through the pre-amplifier facilitates faster and more reliable sensing of the memory cell state. A method comprises receiving first and second signals representative of a logical state stored in a memory cell, pre-amplifying a difference between the first and second signals to produce third and fourth signals having a greater difference, and amplifying the greater difference to more quickly and reliably produce an output indicative of the logical state stored in the memory cell.


William Thompson Photo 9

Variable Resistance Circuit

US Patent:
7180386, Feb 20, 2007
Filed:
Oct 7, 2005
Appl. No.:
11/246469
Inventors:
William N. Thompson - Meridian ID, US
John D. Porter - Meridian ID, US
Larren Gene Weber - Caldwell ID, US
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
H03H 11/30
US Classification:
333 173
Abstract:
A method of finding an unknown value from within a range of values is disclosed that divides the range into weighted subranges and then, beginning with an arbitrary search value within the range, performs a number of simple comparisons to determine the value for each subrange that will result in a match with the target value. This method can also detect those cases where the target value lies outside the range. In one embodiment, the method of finding an unknown value within a range of values is applied to impedance matching. In this embodiment, the output impedance of a pin on an integrated circuit is automatically matched to the impedance of the load connected to it. The output driver has a controllable impedance that can be adjusted within a specific range of impedances to match the external load impedance it is to drive.


William Thompson Photo 10

Latch-Up Prevention For Memory Cells

US Patent:
2005028, Dec 29, 2005
Filed:
Aug 31, 2005
Appl. No.:
11/216220
Inventors:
John Porter - Meridian ID, US
William Thompson - Meridian ID, US
International Classification:
H01L021/8234, H01L021/8238
US Classification:
438238000, 438199000, 438210000, 438202000
Abstract:
An SRAM memory cell is provided having a pair of cross-coupled CMOS inverters. The sources of the pull-up transistors forming each of the CMOS inverters are coupled to Vthrough parasitic resistance of the substrate in which each is formed. The source of the p-type pull-up transistor is therefore always at a potential less than or equal to the potential of the N-well such that the emitter-base junction of the parasitic PNP transistor cannot become forward biased and latch-up cannot occur.