WILLIAM E JOHNSON
Electrician at Lamar Blvd, Austin, TX
License number
Texas 15691
Expiration Date
Apr 22, 2017
Category
Master Electrician
Address
Address
3005 S Lamar Blvd STE D109, Austin, TX 78704
Phone
(512) 791-3525
Professional information
William Johnson - Austin, TX
Work:
THE UNIVERSITY OF TEXAS AT AUSTIN - Austin, TX
Senior IT Specialist - Division of Diversity and Cultural Engagement The University of Texas at Austin - Austin, TX
Desktop Support Specialist - Information Technology Services THE GEORGE WASHINGTON UNIVERSITY - Washington, DC
Senior Programmer/Analyst - Academic Technologies The George Washington University - Washington, DC
Instructional Technology Specialist - Law School THE UNIVERSITY OF TEXAS AT AUSTIN - Austin, TX
Web Developer - School of Architecture QUIOS, INC - San Francisco, CA
Senior Customer Support WAGTECH SOUND PRODUCTIONS - Silver Spring, MD
Sound Engineer DROPOUT RECORDS - Albuquerque, NM
Co-Owner, Purchaser
Senior IT Specialist - Division of Diversity and Cultural Engagement The University of Texas at Austin - Austin, TX
Desktop Support Specialist - Information Technology Services THE GEORGE WASHINGTON UNIVERSITY - Washington, DC
Senior Programmer/Analyst - Academic Technologies The George Washington University - Washington, DC
Instructional Technology Specialist - Law School THE UNIVERSITY OF TEXAS AT AUSTIN - Austin, TX
Web Developer - School of Architecture QUIOS, INC - San Francisco, CA
Senior Customer Support WAGTECH SOUND PRODUCTIONS - Silver Spring, MD
Sound Engineer DROPOUT RECORDS - Albuquerque, NM
Co-Owner, Purchaser
Education:
Western Governors University - Salt Lake City, UT
B.S. in Information Technology University of New Mexico - Albuquerque, NM
Coursework in Theatre Set Design and Technology Game Institute - Washington, DC
Game Development (Self-Study)
B.S. in Information Technology University of New Mexico - Albuquerque, NM
Coursework in Theatre Set Design and Technology Game Institute - Washington, DC
Game Development (Self-Study)
Skills:
System Management: Absolute Manage, Microsoft Deployment Toolkit (MDT), Microsoft System Center Configuration Manager (SCCM), Microsoft Windows Automated Toolkit (WAIK), Sassafras Keyserver, Novell Zenworks, Faronics Deep Freeze, Acronis True Image, Symantec Ghost, DeployStudio Business: MS Office Suite (PC/Mac), SQL Server, Filemaker Pro, MySQL, DB2, Google Apps Media: Audacity, Sound Studio, Ableton Live Suite, Avid Pro Tools, Apple Logic Pro, Adobe Creative Suite, Reaper, Sony Sound Forge, Apple Final Cut Pro Virtualization: VMware Server, VMware Workstation, VMWare Fusion, VirtualBox, Parallels Workstation, VMware vSphere Client Operating Systems: Windows XP/7/8, Windows Server [] Mac OSX, Linux Programming and Frameworks: HTML, CSS, Javascript, PHP, SQL, Visual Basic, Batch Scripting, Wordpress, Amazon Web Services Networking and Communications: TCP/IP, LAN/WAN, SMTP, DNS, DHCP, ISDN, WINS, DMZ, HTTP, FTP, Samba, Cisco Call Manager Hardware: PC/Apple platforms + components, servers, scanners, printers, mobile devices Media Hardware: Crestron and AMX control systems, audio mixing consoles, equalizers, compressors, effect processors, amplification, microphones, video processors/scalars/switchers
William Johnson - Austin, TX
Work:
Brentwood Christian School
SUBSTITUTE TEACHER Data Recognition Corporation, Target Stores, HEB, Montgomery Ward Store, and SIC Finance - Austin, TX
CUSTOMER SERVICE Austin Independent School District - Austin, TX
TEACHER Texas Rehabilitation Commission - Austin, TX
DISABILITY EXAMINER Job placement and Counseling, Gary Job Corps Center - San Marcos, TX
counselor
SUBSTITUTE TEACHER Data Recognition Corporation, Target Stores, HEB, Montgomery Ward Store, and SIC Finance - Austin, TX
CUSTOMER SERVICE Austin Independent School District - Austin, TX
TEACHER Texas Rehabilitation Commission - Austin, TX
DISABILITY EXAMINER Job placement and Counseling, Gary Job Corps Center - San Marcos, TX
counselor
Education:
Southwest Texas State University - San Marcos, TX
21 hours toward Master's in Counseling and Guidance Southwest Texas State University - San Marcos, TX
Bachelor's
21 hours toward Master's in Counseling and Guidance Southwest Texas State University - San Marcos, TX
Bachelor's
Skills:
IBM PC , Apple computers and MS word
External Memory Accessing System
US Patent:
5210841, May 11, 1993
Filed:
Jan 30, 1990
Appl. No.:
7/472099
Inventors:
William M. Johnson - Austin TX
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
G06F 1200, G06F 1210, G06F 934
US Classification:
395400
Abstract:
A new and improved external memory accessing system for use in a microprocessor. The system includes a physical address cache for storing a plurality of entries including register numbers and corresponding translated external memory address locations which were used for execution of previous load instructions. The system further includes means responsive to a current load instruction for determining if the address of the register specified in the load instruction is within the physical address cache and means for conveying to the external memory, at the beginning of the execution stage of the load instruction, a previously translated external memory physical address corresponding to a specified register stored in the physical address cache. Also disclosed is a new and improved address generator for generating a new translated external memory physical address which is conveyed to the external memory and to the physical address cache for updating the physical address cache.
Processing System For Providing An In Circuit Emulator With Processor Internal State
US Patent:
5357626, Oct 18, 1994
Filed:
Oct 20, 1993
Appl. No.:
8/139607
Inventors:
William M. Johnson - Austin TX
David B. Witt - Austin TX
David B. Witt - Austin TX
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
G06F 1100, G01R 3128
US Classification:
395500
Abstract:
A processing system is configured for providing an external in circuit emulator with an internal execution state resulting from the execution by a first processor of an internal instruction stored in an internal instruction cache. The processing system includes a second processor which includes an internal instruction cache for also storing the internal instructions. The second processor is coupled to the first processor in a master/slave configuration to enable the second processor to duplicate the instruction executions of the first processor. The second processor includes an output for providing the internal execution state which is coupled to the in circuit emulator by an external address bus for providing the internal execution parameter to the in circuit emulator.
High Performance Superscalar Microprocessor Including A Circuit For Converting Cisc Instructions To Risc Operations
US Patent:
5867682, Feb 2, 1999
Filed:
Feb 9, 1996
Appl. No.:
8/599696
Inventors:
David B. Witt - Austin TX
William M. Johnson - Austin TX
William M. Johnson - Austin TX
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
G06F 930
US Classification:
395386
Abstract:
A superscalar microprocessor is provided which includes a integer functional unit and a floating point functional unit that share a high performance main data processing bus. The integer unit and the floating point unit also share a common reorder buffer, register file, branch prediction unit and load/store unit which all reside on the same main data processing bus. Instruction and data caches are coupled to a main memory via an internal address data bus which handles communications therebetween. An instruction decoder is coupled to the instruction cache and is capable of decoding multiple instructions per microprocessor cycle. Instructions are dispatched from the decoder in speculative order, issued out-of-order and completed out-of-order. Instructions are retired from the reorder buffer to the register file in-order. The functional units of the microprocessor desirably accommodate operands exhibiting multiple data widths.
System For Reducing Delay For Execution Subsequent To Correctly Predicted Branch Instruction Using Fetch Information Stored With Each Block Of Instructions In Cache
US Patent:
RE35794, May 12, 1998
Filed:
Aug 4, 1994
Appl. No.:
8/285520
Inventors:
William M. Johnson - Austin TX
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
G06F 938
US Classification:
395586
Abstract:
A super-scaler processor is disclosed wherein branch-prediction information is provided within an instruction cache memory. Each instruction cache block stored in the instruction cache memory includes branch-prediction information fields in addition to instruction fields, which indicate the address of the instruction block's successor and information indicating the location of a branch instruction within the instruction block. Thus, the next cache block can be easily fetched without waiting on a decoder or execution unit to indicate the proper fetch action to be taken for correctly predicted branching.
Processor Configured To Selectively Cancel Instructions From Its Pipeline Responsive To A Predicted-Taken Short Forward Branch Instruction
US Patent:
6256728, Jul 3, 2001
Filed:
Jul 6, 1998
Appl. No.:
9/110519
Inventors:
David B. Witt - Austin TX
William M. Johnson - Austin TX
William M. Johnson - Austin TX
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
G06F 1500
US Classification:
712236
Abstract:
A processor is configured to detect a branch instruction have a forward branch target address within a predetermined range of the branch fetch address of the branch instruction. If the branch instruction is predicted taken, instead of canceling subsequent instructions and fetching the branch target address, the processor allows sequential fetching to continue and selectively cancels the sequential instructions which are not part of the predicted instruction sequence (i. e. the instructions between the predicted taken branch instruction and the target instruction identified by the forward branch target address). Instructions within the predicted instruction sequence which may already have been fetched prior to predicting the branch instruction taken may be retained within the pipeline of the processor, and yet subsequent instructions may be fetched.
Prefetch Buffer For Storing Instructions Prior To Placing The Instructions In An Instruction Cache
US Patent:
5845101, Dec 1, 1998
Filed:
May 13, 1997
Appl. No.:
8/855099
Inventors:
William M. Johnson - Austin TX
Thang M. Tran - Austin TX
Matt T. Gavin - Austin TX
Mike Pedneau - Austin TX
Thang M. Tran - Austin TX
Matt T. Gavin - Austin TX
Mike Pedneau - Austin TX
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
G06F 930
US Classification:
395383
Abstract:
A microprocessor is configured to speculatively fetch cache lines of instruction bytes prior to actually detecting a cache miss for the cache lines of instruction bytes. The bytes transferred from an external main memory subsystem are stored into one of several prefetch buffers. Subsequently, instruction fetches may be detected which hit the prefetch buffers. Furthermore, predecode data may be generated for the instruction bytes stored in the prefetch buffers. When a fetch hit in the prefetch buffers is detected, predecode data may be available for the instructions being fetched. The prefetch buffers may each comprise an address prefetch buffer included within an external interface unit and an instruction data prefetch buffer included within a prefetch/predecode unit. The external interface unit maintains the addresses of cache lines assigned to the prefetch buffers in the address prefetch buffers. Both the linear address and the physical address of each cache line is maintained.
Automatic Fan Speed Control
US Patent:
5249741, Oct 5, 1993
Filed:
May 4, 1992
Appl. No.:
7/878115
Inventors:
William R. Bistline - Austin TX
William C. Johnson - Austin TX
James M. Peterson - Austin TX
William C. Johnson - Austin TX
James M. Peterson - Austin TX
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H02H 318
US Classification:
236 493
Abstract:
A method of cooling a computer having a plurality of components and at least one variable rate cooling unit including the steps of obtaining a cooling requirement for at least one of the components and varying the rate of at least one of the cooling units based on the obtained cooling requirements. In addition an apparatus for cooling a computer having a plurality of components, the apparatus including at least one variable rate cooling unit, an apparatus for obtaining a cooling requirement for at least one of the components, and an apparatus for varying the rate of at least one of the cooling units based on the obtained cooling requirements.
High Performance Load/Store Functional Unit And Data Cache
US Patent:
6298423, Oct 2, 2001
Filed:
Aug 26, 1996
Appl. No.:
8/703299
Inventors:
William M. Johnson - Austin TX
David B. Witt - Austin TX
Murali Chinnakonda - Austin TX
David B. Witt - Austin TX
Murali Chinnakonda - Austin TX
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
G06F 1202
US Classification:
711154
Abstract:
A load/store functional unit and a corresponding data cache of a superscalar microprocessor is disclosed. The load/store functional unit includes a plurality of reservation station entries which are accessed in parallel and which are coupled to the data cache in parallel. The load/store functional unit also includes a store buffer circuit having a plurality of store buffer entries. The store buffer entries are organized to provide a first in first out buffer where the outputs from less significant entries of the buffer are provided as inputs to more significant entries of the buffer.