WILLIAM CHEN
Pilots at Santa Paula Ave, Sunnyvale, CA

5179716, Jan 12, 1993

Jun 21, 1989

7/370148

Om P. Agrawal - San Jose CA
Arthur H. Khu - San Mateo CA
William Chen - Sunnyvale CA

Advanced Micro Devices, Inc. - Sunnyvale CA

G06F 922

395800

A programmable controller which combines microaddress control logic, memory, a microinstruction decoder, and I/O into a unitary, integrated device. The microaddress control logic is responsive to sequencing signals developed by the microinstruction decoder, and includes an address generator which develops the program address. The memory, which can be either PROM or RAM, is addressed by the address and outputs a microinstruction word to a pipeline register. The microinstruction word has an internal field which is coupled to inputs of the microaddress control logic and the microinstruction decoder, and a control field which is coupled to an output buffer. The output buffer includes multiplexers which permit either the program count or the control field to be multiplexed to the output pins of the device. When the program address is multiplexed to the output pins, the programmable controller can address external memory devices.

6505345, Jan 7, 2003

Jan 18, 2000

09/483879

William Y. Chen - Sunnyvale CA

Intel Corporation - Santa Clara CA

G06F 945

717154, 712216

An optimization process is disclosed. The process first finds a parallel compare sequence in a program flow, for example using a flow graph. The guarding predicate (gp) is obtained for the compares. If a new dominating predicate (dp) can be found, the process proceeds to determining if compares for the dp generate the correct or needed initial value for the gp. If there are free result slots available, the proper compares are generated and folded into the initialization. If no free slots are available, it is determined if there is a use of a gp between the dp and gp. If not, the dp is renamed to gp, and the proper compares are generated and folded into the initialization. If there is such a use, the guarding predicate of the compares is found and the process reiterates until it ends with the failure to find a new dominating predicate dp.

6732356, May 4, 2004

Mar 31, 2000

09/540145

William Y. Chen - Sunnyvale CA

Intel Corporation - Santa Clara CA

G06F 945

717156, 717152, 717153

Systems and methods are provided through which compare instructions in computer code are eliminated partially resolving the predicate of the compare instructions. Partially resolved predicates are used to reduce the number of compares generated during the prediction phase of the compiler. In a partially resolved predicate, the predicate name is defined along the same paths as the fully resolved predicate counterpart, but it can be used to guard a subset of the instructions of the fully resolved predicate name. A partially resolved predicate is generated for predicate names which are only valid in a restricted control flow region. One or more of the control flow edges are ignored when computing control dependence. The predicate name relies partially on the actual ignored control flow edge to prevent incorrect usage of the predicate name.

6631460, Oct 7, 2003

Apr 27, 2000

09/559508

Dale C. Morris - Menlo Park CA
William R. Bry - Saratoga CA
Alan H. Karp - Palo Alto CA
William Chen - Sunnyvale CA

Institute for the Development of Emerging Architectures, L.L.C. - Cupertino CA

G06T 930

712217, 712228, 712216

A computer system includes physical registers holding data for compiled programs and a portion of the physical registers form a register stack which wraps around when full. An N-bit current wraparound count state tracks physical register remapping events which cause the register stack to wraparound or unwrap. An advanced load address table (ALAT) has entries corresponding to load instructions, each entry has at least one memory range field defining a range of memory locations accessed by a corresponding load instruction, a physical register number field corresponding to a physical register accessed in the corresponding load instruction, and an N-bit register wraparound field which corresponds to the N-bit current wraparound count state for the corresponding load instruction. A check instruction accesses the ALAT to determine whether a store instruction and an advanced load instruction, which is scheduled before the store instruction, potentially accessed a common memory location. After the execution of the store instruction, an absence of an entry corresponding to the load instruction in the ALAT indicates that a common memory location may have been accessed by the store and load instructions.

6637026, Oct 21, 2003

Mar 1, 2000

09/516102

William Y. Chen - Sunnyvale CA

Intel Corporation - Santa Clara CA

G06F 945

717151, 717144, 717150, 717155, 717156, 717159, 717161, 709103, 709104, 712226

When compiling software for a processor that supports predication, an alerting instruction can be inserted to alert a global register allocator to map particular virtual predicates into the same physical registers. Redundant predicate generating instructions are removed from the resulting program. The alerting instruction can be a predicate copy pseudo-opcode. When the register allocator maps the virtual predicates into the same physical register, the predicate copy pseudo-opcode is removed. When the register allocator does not map the virtual predicates to the same physical register, the predicate copy pseudo-opcode is replaced by an instruction that will perform a predicate copy.

6631465, Oct 7, 2003

Jun 30, 2000

09/607684

William Y. Chen - Sunnyvale CA

Intel Corporation - Santa Clara CA

G06F 938

712234, 712241, 717159, 717160

A method and apparatus that provides instruction re-alignment using a branch on a falsehood of a qualifying predicate. A complementary predicate related to a qualifying predicate is determined to be available. Instructions are re-aligned using a branch on a falsehood of the qualifying predicate if the complementary predicate is not available. Thus, a complementary predicate does not have to be generated to re-align instructions if no complementary predicate is available for the qualifying predicate.

5903749, May 11, 1999

Jul 2, 1996

8/675170

H. Roland Kenner - Cupertino CA
Alan Karp - Palo Alto CA
William Chen - Sunnyvale CA

Institute for the Development of Emerging Architecture, L.L.C. - Cupertino CA

G06F13/00

395567

A method and apparatus for implementing check instructions that allow for the reuse of memory conflict information if no memory conflict occurs. According to one aspect of the invention, a machine-readable medium having stored thereon data representing sequences of instructions is described. When executed by a computer system, the sequences of instructions cause the computer system to perform a series of steps. One of these steps involves preloading one of a set of registers data retrieved from a memory starting at a first address. Another of these steps involves storing memory conflict information representing the first address. This memory conflict information is later used for determining if a memory conflict has occurred. Another of these steps involves storing data at a second address in the memory. Yet another of these steps involves determining if a memory conflict has occurred between the first address and the second address using the previously stored memory conflict information.

8020155, Sep 13, 2011

Nov 28, 2006

11/605540

Jiwei Lu - Pleasanton CA, US
William Yu-Wei Chen - Sunnyvale CA, US

Oracle America, Inc. - Redwood City CA

G06F 9/45

717153, 717159, 717162

A mechanism is provided for managing the referencing of at least two versions of a function. A first version is a single threaded version that does not ensure multi-thread safety. A second version is a multi threaded version that does ensure multi-thread safety. The mechanism determines whether a set of executable code (e. g. a program) is currently executing in single-threaded mode or multi-threaded mode. If the executable code is executing in single-threaded mode, then the mechanism causes the executable code to reference the first version of the function. If the executable code is executing in multi-threaded mode, then the mechanism causes the executable code to reference the second version of the function. By doing so, the mechanism ensures that the additional overhead of ensuring multi-thread safety is incurred only when it is needed. In this manner, the mechanism makes execution of the function more optimal.

5694577, Dec 2, 1997

Jun 6, 1995

8/470825

Tokuzo Kiyohara - Osaka-fu, JP
Wen-mei W. Hwu - Champaign IL
William Chen - Sunnyvale CA

Matsushita Electric Industrial Co., Ltd. - Osaka-fu
The Board of Trustees of the University of Illinois - Urbana IL

G06F 1300, G06F 1200

395494

An apparatus is provided, for use in a computer having a register bank and a device for operand fetch and instruction execution, for monitoring a store address to maintain coherency of preloaded data that is fetched by a load operation and should be effected by at least one subsequent store operation. The apparatus includes an address register bank having entries for holding the address of a load having loaded data which should be affected by at least one subsequent store operation. Each of the entries has associated therewith a pre-load flag and a type field, the pre-load flag being set when the load is executed and reset when there is no need to be affected by a subsequent store operation. The apparatus is further configured to compare the address held in the register bank with the address of a subsequent store operation in consideration of the access type held in the type of field when the pre-load flag is set, and to reset the pre-load flag when special operation which terminate monitoring addresses are detected or the value is updated by non-preload operations. Each of the entries has further associated therewith a retry flag set when the preloaded data is invalid and reloading is required at the point of usage.