William B Lynch
Real Estate Appraisers in Summit, NJ

4824796, Apr 25, 1989

Jul 10, 1987

7/077953

Tzu-Yin Chiu - Marlboro NJ
Gen M. Chin - Marlboro NJ
Ronald C. Hanson - Middletown NJ
Maureen Y. Lau - Keyport NJ
Kwing F. Lee - Aberdeen NJ
Mark D. Morris - Freehold NJ
Alexander M. Voshchenkov - Freehold NJ
Avinoam Kornblit - Highland Park NJ
Joseph Lebowitz - Watchung NJ
William T. Lynch - Summit NJ

American Telephone and Telegraph Company - New York NY
AT&T Bell Laboratories - Murray Hill NJ

H01L 2170, H01L 2700

437 57

A process for creating bipolar and CMOS transistors on a p-type silicon substrate is disclosed. The silicon substrate has typical n+ buried wells and field oxide regions to isolate the individual transistor devices. In accordance with the process, stacks of material are created over the gate elements of the CMOS devices and over the emitter elements of the bipolar transistors. The stacks of material over the gate elements have a silicon dioxide gate layer in contact with the epitaxial layer of the substrate, and the stacks of material over the emitter elements have a polycrystalline silicon layer in contact with the epitaxial layer. Walls of silicon dioxide are created around the stacks in order to insulate the material within the stacks from the material deposited outside of the walls. Polycrystalline silicon in contact with the epitaxial layer is deposited outside the walls surrounding the stacks. All polycrystalline silicon layers in contact with the epitaxial layer are implanted with appropriate dopants such that these layers serve as reservoirs of dopant in order to simultaneously create the source and drain elements of the CMOS devices and the emitter elements of the bipolar devices during a heating step in the process.

5063422, Nov 5, 1991

Apr 26, 1990

7/515550

Steven J. Hillenius - Summit NJ
Joseph Lebowitz - Watchung NJ
Ruichen Liu - Warren NJ
William T. Lynch - Summit NJ

AT&T Bell Laboratories - Murray Hill NJ

H01L 2910, H01L 2702, H01L 2348

357 233

In CMOS based integrated circuits, stricter design rules require source and drain junctions shallower than 2500. ANG. By using a specific device configuration, a shallow junction is obtainable while resistance to latch-up is improved and other electrical properties, e. g. , low leakage current, are maintained. To achieve this result the p-channel device should have an activation energy of the junction reverse leakage current region less than 1. 12 eV, with a junction dopant region shallower than 1200. ANG. and a monotonically decreasing junction dopant profile.

4992394, Feb 12, 1991

Jul 31, 1989

7/387721

Robert L. Kostelak - Morris Plains NJ
William T. Lynch - Summit NJ
Sheila Vaidya - Watchung NJ

AT&T Bell Laboratories - Murray Hill NJ

H01L 2170

437229

In order to reduce alignment errors arising in the fabrication of semiconductor integrated circuits using electron beam lithography, enhanced registration marks--(i. e. , registration marks that are more easily and accurately detectable by the electron beam)--are formed at the edges of oxide layers, located at the surface of a silicon body, by means of forming metal silicide layers having edges coincident with the edges of the oxide layers. Advantageously, the enhancing of the registgration marks by forming the metal silicide is performed subsequent to any high temperature processing steps, whereby the integrity of the marks is maintained.

4825278, Apr 25, 1989

Mar 2, 1987

7/020771

Steven J. Hillenius - Summit NJ
William T. Lynch - Summit NJ
Lalita Manchanda - North Plainfield NJ

American Telephone and Telegraph Company AT&T Bell Laboratories - Murray Hill NJ

H01L 2940

357 53

Disclosed are semiconductor devices and circuits which are highly resistant to the effects of radiation. A thin conductive layer, which is biased at substrate potential, and a thin oxide are provided under the usual field oxide of the devices. The conductive layer shields the semiconductor substrate from the effects of charge generation in the field oxide due to radiation absorption.

4694561, Sep 22, 1987

Nov 30, 1984

6/676677

Joseph Lebowitz - Watchung NJ
William T. Lynch - Summit NJ

American Telephone and Telegraph Company, AT&T Bell Laboratories - Murray Hill NJ

H01L 2172, H01L 21385

437 52

A trench version of a high-capacitance (Hi-C) capacitor for a dynamic random-access-memory (DRAM) cell is made utilizing a modified version of the doping technique described in U. S. Pat. No. 4,471,524 and 4,472,212. A shallow highly doped trench region is thereby formed. At the same time, selected lateral surface portions of the structure are also thereby highly doped. These surface portions permit a direct electrical connection to be easily made between the capacitor and a subsequently formed adjacent access transistor.

4914502, Apr 3, 1990

Jan 29, 1988

7/147038

Joseph Lebowitz - Watchung NJ
William T. Lynch - Summit NJ

AT&T Bell Laboratories - Murray Hill NJ

H01L 2348

357 68

In order to reduce parasitic capacitive cross-coupling in an integrated circuit, metallization lines in an array--for example, an array of word lines, of bit lines, or of bus interconnects--are geometrically arranged in a systematically progressive laterally (sidewise) marching sequence, whereby the identity of the lines located on either side of a given line keeps changing.

4485550, Dec 4, 1984

Jul 23, 1982

6/401142

Conrad J. Koeneke - Fanwood NJ
Martin P. Lepselter - Summit NJ
William T. Lynch - Summit NJ

AT&T Bell Laboratories - Murray Hill NJ

H01L 2128

29571

Schottky-barrier MOS and CMOS devices are significantly improved by selectively doping the regions surrounding the Schottky-barrier source and drain contacts. For p-channel devices, acceptor doping is carried out in either a one-step or a two-step ion implantation procedure. For n-channel devices, donor doping is carried out in a two-step procedure. In each case, current injection into the channel is enhanced and leakage to the substrate is reduced while still maintaining substantial immunity to parasitic bipolar transistor action (MOS devices) and to latchup (CMOS devices).

4822754, Apr 18, 1989

Jun 12, 1984

6/619892

William T. Lynch - Summit NJ
Frederick Vratny - Berkeley NJ

American Telephone and Telegraph Company, AT&T Bell Laboratories - Murray Hill NJ

H01L 21225

437193

A method of fabricating FETs to reduce parasitics. Contact is made to the source and drain regions through a polycrystalline silicon runner which is aligned with the edge of the gate electrode. This is accomplished by providing a multi-level electrode structure including a gate electrode and depositing the polycrystalline silicon layer over the device. The polycrystalline silicon is rendered selectively removable in the portion overlying the gate electrode. When this portion is removed, the remaining polycrystalline is aligned with the gate.

4794091, Dec 27, 1988

Nov 17, 1987

7/121556

William T. Lynch - Summit NJ

American Telephone and Telegraph Company, AT&T Bell Laboratories - Murray Hill NJ

H01L 21302

437 48

Parallel elongated trenches in a silicon substrate are utilized to form multiple distinct memory cell capacitors on each continuous wall of each trench. Chanstops are formed between adjacent capacitors to achieve electrical isolation. A separate word line overlies each trench wall and is connected via respective MOS transistors to the spaced-apart capacitors formed on the wall. A reliable high-density memory characterized by excellent performance is thereby realized.

4091360, May 23, 1978

Sep 1, 1976

5/719445

William Thomas Lynch - Summit NJ

Bell Telephone Laboratories, Incorporated - Murray Hill NJ

G11C 700

340166R

In MOS circuitry, such as a dynamic MOS random access memory, precharge circuitry, consisting of six p-channel MOS transistors and a seventh p-channel MOS transistor connected as a capacitor, facilitates a two step charging process that initially lowers the potential of a first circuit node from a high potential to a value approximately one threshold voltage above an available low level power supply potential and then further lowers the potential of the circuit node to a value below that of the available low level power supply potential. A single voltage pulse and the complement thereof are the only input signals required. Normal threshold voltage losses of MOS transistors can thus be effectively eliminated and noise margins thereby improved.