William Arthur Edwards
Engineers in Livermore, CA

License number
Colorado 38800
Issued Date
Dec 3, 2004
Renew Date
Nov 1, 2015
Expiration Date
Oct 31, 2017
Type
Professional Engineer
Address
Address
PO Box 808, Livermore, CA 94551

Professional information

William Edwards Photo 1

Electrical Connector Having Enhanced Strain Relief For Signal-Sensitive Electronic Equipment

US Patent:
6777619, Aug 17, 2004
Filed:
Feb 4, 2003
Appl. No.:
10/358744
Inventors:
Curt Von Badinski - San Jose CA
William Edwards - Livermore CA
Michael Kornprobst - Pleasanton CA
Bradley Erickson - San Carlos CA
Samir Vasavda - Fremont CA
Assignee:
Cisco Technology, Inc. - San Jose CA
International Classification:
H01R 13622
US Classification:
174135, 439362
Abstract:
An electrical connector comprises a housing configured to house an interconnect mechanism, which defines an on-axis plane that is coplanar with the long axis of the interconnect mechanism. The housing includes at least two receptacles for accepting coupling mechanisms for interconnecting the connector to an electronic component. The centerline axis of at least one of the receptacles is parallel to the on-axis plane and offset from the on-axis plane. In one embodiment, the housing further comprises a first lip having a long axis that is parallel with the on-axis plane, such that when the connector is interconnected to an electronic component, the first lip applies an off-axis force to the component. The off-axis force is applied to the component along a first off-axis that is different than the on-axis. Consequently, resistance to deflection of the connector is provided, as is a more reliable contact engagement between the connector and the interconnected electronic component.


William Edwards Photo 2

William Edwards - Kailua-Kona, HI

Work:
Lawrence Livermore National Laboratory - Weapons and Complex Integration
Quality Manager - Pit Surveillance Program
LLNL - Global Security
Quality Engineer, Global Security, N Program, DNDO Red Team
LLNL - Global Security - Livermore, CA
QA/Data Package Validation Manager
LLNL - Global Seurity
QA/Data Package Validation Manager
LLNL - Chemistry and Materials Sciences - Livermore, CA
Lead Chemist, Hazardous Waste Radiation Laboratory (HWRL) and Chemical Coordinator for the Chemistry and Material Science (CMS) Directorate
LLNL - Hazardous Waste Radiation Laboratory - Livermore, CA
Quality Manager, Radiation Analytical Sciences
Various Nuclear Power Plants
Consultant/Senior QA Engineer and Chemist
Education:
Georgia State University - Atlanta, GA
B. S. in Biology


William Edwards Photo 3

Ac/Dc Power Accommodation Method And Apparatus For Networking/Telecommunications Devices

US Patent:
6347949, Feb 19, 2002
Filed:
Jun 30, 2000
Appl. No.:
09/608491
Inventors:
William F. Edwards - Livermore CA
Earl Devenport - San Jose CA
Robert Gregory Twiss - Chapel Hill NC
Assignee:
Cisco Technology Inc. - San Jose CA
International Classification:
H01R 2900
US Classification:
439170
Abstract:
An adaptor is provided for effectively converting an opening in the chassis or box of a router (or similar device) from an opening which accommodate a power entry component for a first power type to accommodate a power entry component for a second power type. In one aspect, an adaptor fits in a panel opening which is sized and shaped to receive an IEC-compliant AC power entry component. The adaptor has a window or opening which accommodates, e. g. a four-wire DC power entry component. In one aspect, an adaptor couples to screw holes, such as on either side of an RPS coupler and also receives a standard ground wire log, preferably forming a conductive path from the lug to the screw holes.


William Edwards Photo 4

Holder For Closely-Positioned Multiple Gbic Connectors

US Patent:
6366471, Apr 2, 2002
Filed:
Jun 30, 2000
Appl. No.:
09/607973
Inventors:
William F. Edwards - Livermore CA
Earl Devenport - San Jose CA
Robert Gregory Twiss - Chapel Hill NC
Assignee:
Cisco Technology, Inc. - San Jose CA
International Classification:
H05K 714
US Classification:
361796, 361753, 361807, 439 79, 385 92
Abstract:
A frame or similar structure is used for positioning two stacked GBIC connectors within a 1 RU form factor height of a router or similar network device. In one aspect, the frame can be constructed, assembled and/or mounted in the absence of a need for screws or similar connectors and/or tools. Hooks, latches, engaging teeth and the like can engage sections of a chassis base plate, to position the GBIC connectors preferably within a cutout formed in a motherboard. Use of a flex circuit for connecting the GBIC connectors to a motherboard avoids the requirement for high-precision placement for positioning.


William Edwards Photo 5

Carrier Card Converter For 10 Gigabit Ethernet Slots

US Patent:
2006021, Sep 28, 2006
Filed:
Mar 25, 2005
Appl. No.:
11/090776
Inventors:
Alan Yee - Los Gatos CA, US
Eric Wiles - Sunnyvale CA, US
James Rivers - Saratoga CA, US
Sandeep Patel - Los Gatos CA, US
William Edwards - Livermore CA, US
Jeffrey Provost - Campbell CA, US
International Classification:
H01R 12/00
US Classification:
439066000
Abstract:
A carrier module is physically compatible with a XENPAK/X2 10 GE slot and includes a socket for accepting a non-XENPAK/X2 module and interface circuitry for providing appropriate signals to a XENPAK/X2 70-pin connector on an interior side of the carrier module. The carrier module includes a cookie, accessible by host software, identifying the type of carrier module and non-XENPAK/X2 module accepted by the carrier card.


William Edwards Photo 6

Closely-Positioned Multiple Gbic Connectors

US Patent:
6272019, Aug 7, 2001
Filed:
Jun 11, 1999
Appl. No.:
9/330434
Inventors:
William F. Edwards - Livermore CA
Frederick Roland Schindler - Sunnyvale CA
Robert Gregory Twiss - Portola Valley CA
Assignee:
Cisco Technology Inc. - San Jose CA
International Classification:
H05K 702
US Classification:
361760
Abstract:
GBIC frames are mounted with respect to one or another or with respect to the printed circuit board so as to facilitate space sufficiency, e. g. of a front or other panel. In one aspect two GBIC frames are mounted in back-to-back fashion on opposite surfaces of a mounting plate of preferably minimal thickness. Plate cut-outs are positioned to accommodate frame feet or other mounting structures in a fashion off-set, on opposite faces, to avoid interference between frame legs. In one aspect, portions of GBICs and frames are received in cut-out or other edges of a PCB so that GBICs in frames straddle a major surface of a PCB to reduce height for accommodating 1RU or other form factors while increasing space efficiency.


William Edwards Photo 7

Pulsed Particle Beam Vacuum-To-Air Interface

US Patent:
4785254, Nov 15, 1988
Filed:
Jun 18, 1987
Appl. No.:
7/063602
Inventors:
Gilbert E. Cruz - Pleasanton CA
William F. Edwards - Livermore CA
Assignee:
The United States of America as represented by The United States
Department of Energy - Washington DC
International Classification:
H05H 710
US Classification:
328233
Abstract:
A vacuum-to-air interface (10) is provided for a high-powered, pulsed particle beam accelerator. The interface comprises a pneumatic high speed gate valve (18), from which extends a vacuum-tight duct (26), that termintes in an aperture (28). Means (32, 34, 36, 38, 40, 42, 44, 46, 48) are provided for periodically advancing a foil strip (30) across the aperture (28) at the repetition rate of the particle pulses. A pneumatically operated hollow sealing band (62) urges foil strip (30), when stationary, against and into the aperture (28). Gas pressure means (68, 70) periodically lift off and separate foil strip (30) from aperture (28), so that it may be readily advanced.


William Edwards Photo 8

Dual-Stacked 10 Gigabit X2 Uplinks In A Single Rack Unit Switch

US Patent:
2006004, Mar 2, 2006
Filed:
Aug 30, 2004
Appl. No.:
10/931124
Inventors:
Samir Vasavda - Fremont CA, US
William Edwards - Livermore CA, US
Michael Kornprobst - Pleasanton CA, US
David Nelsen - Fremont CA, US
International Classification:
H05K 7/14, H05K 7/10
US Classification:
361796000, 361785000
Abstract:
A system for providing dual 10 GB uplinks in the front side of a single rack unit switch that stacks two MSA X2 I/O devices in a limited space. In one embodiment the two X2 I/O devices are mounted on opposite sides of a single circuit board positioned above the motherboard.