WILLIAM ANDERSON, D.M.D.
Dentist in El Paso, TX
License number
Texas 25378
Category
Dentist
Type
General Practice
Address
Address
2
1502 N Zaragosa Rd, El Paso, TX 79936
8701 Bluffstone Cv, Austin, TX 78759
8701 Bluffstone Cv, Austin, TX 78759
Phone
(915) 855-4442
Personal information
See more information about WILLIAM ANDERSON at radaris.comName
Address
Phone
509 Grant Cir, Fort Worth, TX 76108
508 E Howard Ln TRLR 550, Austin, TX 78753
501 Judith St, Burleson, TX 76028
5015 Buttonwood Ln, Garland, TX 75043
501 Roland Ln TRLR 13, Kyle, TX 78640
Organization information
See more information about WILLIAM ANDERSON at bizstanding.comWilliam Anderson Trucking
1415 N Campbell St, El Paso, TX 79902
Industry:
Local Trucking Operator
President:
William E. Anderson (President)
Professional information
Method And System For Trusted/Untrusted Digital Signal Processor Debugging Operations
US Patent:
8533530, Sep 10, 2013
Filed:
Nov 15, 2006
Appl. No.:
11/560332
Inventors:
Lucian Codrescu - Austin TX, US
William C. Anderson - Austin TX, US
Suresh Venkumahanti - Austin TX, US
Louis Achille Giannini - Berwyn IL, US
Manojkumar Pyla - San Diego CA, US
Xufeng Chen - San Diego CA, US
William C. Anderson - Austin TX, US
Suresh Venkumahanti - Austin TX, US
Louis Achille Giannini - Berwyn IL, US
Manojkumar Pyla - San Diego CA, US
Xufeng Chen - San Diego CA, US
Assignee:
QUALCOMM Incorporated - San Diego CA
International Classification:
G06F 11/00
US Classification:
714 21, 726 21
Abstract:
Techniques for the design and use of a digital signal processor, including (but not limited to) for processing transmissions in a communications (e. g. , CDMA) system. Trusted and untrusted debugging operational control occurs in operating a core processor associated with the digital signal processor. A debugging process within a debugging mechanism associates with the core processor. The core processor process determines the origin of debugging control as trusted debugging control or untrusted debugging control. In the event of trusted debugging control, the core processor process provides to the trusted debugging control a first set of features and privileges. Alternatively, in the event that debugging control is untrusted debugging control, the core processor process provides the untrusted debugging control a second restricted set of features and privileges, all for maintaining security and proper operation of the core processor process.
Inter-Thread Trace Alignment Method And System For A Multi-Threaded Processor
US Patent:
8484516, Jul 9, 2013
Filed:
Apr 11, 2007
Appl. No.:
11/734199
Inventors:
Louis Achille Giannini - Berwyn IL, US
William Anderson - Austin TX, US
Xufeng Chen - San Diego CA, US
William Anderson - Austin TX, US
Xufeng Chen - San Diego CA, US
Assignee:
QUALCOMM Incorporated - San Diego CA
International Classification:
G06F 11/00
US Classification:
714 45, 714 12, 714 20, 717128
Abstract:
Techniques for the design and use of a digital signal processor, including (but not limited to) for processing transmissions in a communications (e. g. , CDMA) system. Inter-thread trace alignment with execution trace processing includes recording timing data relating to a common predetermined event. Such an event may be the number of cycles since a last thread initiated execution tracing or the number of cycles since all threads terminated execution tracing. The number of cycles at which a thread initiates execution tracing is referenced to the common predetermined event for maintaining the timing of execution tracing. The data relating to the common predetermined event is then updated to associate with the time at which the thread initiated execution tracing. The result is to permit aligning the timing data associated with all threads. Interrelated records permit reconstructing interdependent execution tracing information for threads operating in the multi-threaded processor, as well as synchronizing timing data for all operating threads.
Digital Signal Processor Computation Core With Input Operand Selection From Operand Bus For Dual Operations
US Patent:
7111155, Sep 19, 2006
Filed:
May 12, 2000
Appl. No.:
09/570108
Inventors:
William C. Anderson - Austin TX, US
John Edmondson - Arlington MA, US
Jose Fridman - Brookline MA, US
Marc Hoffman - Mansfield MA, US
Russell L. Rivin - Holliston MA, US
John Edmondson - Arlington MA, US
Jose Fridman - Brookline MA, US
Marc Hoffman - Mansfield MA, US
Russell L. Rivin - Holliston MA, US
Assignee:
Analog Devices, Inc. - Norwood MA
International Classification:
G06F 7/38
US Classification:
712225, 712221, 712 33, 712208, 712226
Abstract:
A computation core includes a computation block, an addressing block and an instruction sequencer, which are coupled to a memory through a memory interface. The computation block includes a register file and dual execution units. The execution units include features for enhanced performance in executing digital signal computations. The computation core is configured for executing digital signal processor instructions and microcontroller instructions, while achieving efficient digital signal processor computation and high code density. A finite impulse response filter algorithm achieves high performance on the dual execution units.
Method And System For Encoding Variable Length Packets With Variable Instruction Sizes
US Patent:
7526633, Apr 28, 2009
Filed:
Mar 23, 2005
Appl. No.:
11/088607
Inventors:
Lucian Codrescu - Austin TX, US
Erich Plondke - Austin TX, US
Muhammad Ahmed - Austin TX, US
William C. Anderson - Austin TX, US
Erich Plondke - Austin TX, US
Muhammad Ahmed - Austin TX, US
William C. Anderson - Austin TX, US
Assignee:
QUALCOMM Incorporated - San Diego CA
International Classification:
G06F 9/30, G06F 15/00
US Classification:
712210, 712209
Abstract:
Techniques for processing transmissions in a communications (e. g. , CDMA) system. The method and system encode and process instructions of mixed lengths (e. g. , 16 bits and 32 bits) and instruction packets including instructions of mixed lengths. This includes encoding a plurality of instructions of a first length and a plurality of instructions of a second length. The method and system encode a header having at least one instruction length bit. The instruction bit distinguishes between instructions of the first length and instructions of the second length for an associated DSP to process in a mixed stream. The method and system distinguish between the instructions of the first length and the instructions of the second length according to the contents of the instruction length bits. The header further includes bits for distinguishing between instructions of varying lengths in an instruction packet.
Register Files For A Digital Signal Processor Operating In An Interleaved Multi-Threaded Environment
US Patent:
2006024, Oct 26, 2006
Filed:
Apr 26, 2005
Appl. No.:
11/115916
Inventors:
Muhammad Ahmed - Austin TX, US
Erich Plondke - Austin TX, US
Lucian Codrescu - Cove Austin TX, US
William Anderson - Austin TX, US
Erich Plondke - Austin TX, US
Lucian Codrescu - Cove Austin TX, US
William Anderson - Austin TX, US
International Classification:
G06F 15/00
US Classification:
712024000
Abstract:
A processor device is disclosed and includes a memory and a sequencer that is responsive to the memory. The sequencer supports very long instruction word (VLIW) type instructions and at least one VLIW instruction packet uses a number of operands during execution. The processor device further includes a plurality of instruction execution units responsive to the sequencer and a plurality of register files. Each of the plurality of register files includes a plurality of registers and the plurality of register files are coupled to the plurality of instruction execution units. Further, each of the plurality of register files includes a number of data read ports and the number of data read ports of each of the plurality of register files is less than the number of operands used by the at least one VLIW instruction packet.
Unified Non-Partitioned Register Files For A Digital Signal Processor Operating In An Interleaved Multi-Threaded Environment
US Patent:
2006023, Oct 12, 2006
Filed:
Apr 11, 2005
Appl. No.:
11/103744
Inventors:
Lucian Codrescu - Austin TX, US
Erich Plondke - Austin TX, US
Muhammad Ahmed - Austin TX, US
William Anderson - Austin TX, US
Taylor Simpson - Austin TX, US
Erich Plondke - Austin TX, US
Muhammad Ahmed - Austin TX, US
William Anderson - Austin TX, US
Taylor Simpson - Austin TX, US
International Classification:
G06F 15/00
US Classification:
712024000
Abstract:
A processor device is disclosed and includes a memory and a sequencer that is responsive to the memory. The sequencer can support very long instruction word (VLIW) instructions and superscalar instructions. The processor device further includes a first instruction execution unit responsive to the sequencer, a second instruction execution unit responsive to the sequencer, a third instruction execution unit responsive to the sequencer, and a fourth instruction execution unit responsive to the sequencer. Further, the processor device includes a plurality of register files and each of the plurality of register files includes a plurality of registers. The plurality of register files are coupled to the sequencer and coupled to the first instruction execution unit, the second instruction execution unit, the third instruction execution unit, and the fourth instruction execution unit.
Processor And Method Of Grouping And Executing Dependent Instructions In A Packet
US Patent:
7523295, Apr 21, 2009
Filed:
Mar 21, 2005
Appl. No.:
11/086475
Inventors:
Lucian Codrescu - Austin TX, US
Erich Plondke - Austin TX, US
Muhammad Ahmed - Austin TX, US
Sujat Jamil - Austin TX, US
William C. Anderson - Austin TX, US
Erich Plondke - Austin TX, US
Muhammad Ahmed - Austin TX, US
Sujat Jamil - Austin TX, US
William C. Anderson - Austin TX, US
Assignee:
QUALCOMM Incorporated - San Diego CA
International Classification:
G06F 9/30, G06F 9/40
US Classification:
712214, 712216, 712218
Abstract:
An interleaved multithreading pipeline operating method comprises reading an instruction packet containing at least two instructions, steering a first instruction of the instruction packet to a first execution unit for execution and generating a first result, steering a second instruction of the instruction packet to a second execution unit for execution using the first result and generating a second result, and storing the second result.
Variable Width Alignment Engine For Aligning Instructions Based On Transition Between Buffers
US Patent:
7360059, Apr 15, 2008
Filed:
Feb 3, 2006
Appl. No.:
11/347097
Inventors:
Thomas Tomazin - Austin TX, US
William C. Anderson - Austin TX, US
Charles P. Roth - Austin TX, US
Kayla Chalmers - Austin TX, US
Juan G. Revilla - Austin TX, US
Ravi P. Singh - Austin TX, US
William C. Anderson - Austin TX, US
Charles P. Roth - Austin TX, US
Kayla Chalmers - Austin TX, US
Juan G. Revilla - Austin TX, US
Ravi P. Singh - Austin TX, US
Assignee:
Analog Devices, Inc. - Norwood MA
International Classification:
G06F 9/00
US Classification:
712204, 712207
Abstract:
In one embodiment, a digital signal processor includes look ahead logic to decrease the number of bubbles inserted in the processing pipeline. The processor receives data containing instructions in a plurality of buffers and decodes the size of a first instruction. The beginning of a second instruction is determined based on the size of the first instruction. The size of the second instruction is decoded and the processor determines whether loading the second instruction will deplete one of the plurality of buffers.
Aligning Instructions Using A Variable Width Alignment Engine Having An Intelligent Buffer Refill Mechanism
US Patent:
7082516, Jul 25, 2006
Filed:
Sep 28, 2000
Appl. No.:
09/675817
Inventors:
Thomas Tomazin - Austin TX, US
William C. Anderson - Austin TX, US
Charles P. Roth - Austin TX, US
Kayla Chalmers - Austin TX, US
Juan G. Revilla - Austin TX, US
Ravi P. Singh - Austin TX, US
William C. Anderson - Austin TX, US
Charles P. Roth - Austin TX, US
Kayla Chalmers - Austin TX, US
Juan G. Revilla - Austin TX, US
Ravi P. Singh - Austin TX, US
Assignee:
Intel Corporation - Santa Clara CA
Analog Devices, Inc. - Norwood MA
Analog Devices, Inc. - Norwood MA
International Classification:
G06F 9/00
US Classification:
712204, 712207
Abstract:
In one embodiment, a digital signal processor includes look ahead logic to decrease the number of bubbles inserted in the processing pipeline. The processor receives data containing instructions in a plurality of buffers and decodes the size of a first instruction. The beginning of a second instruction is determined based on the size of the first instruction. The size of the second instruction is decoded and the processor determines whether loading the second instruction will deplete one of the plurality of buffers.
Large Ram Cache
US Patent:
2012029, Nov 22, 2012
Filed:
May 20, 2011
Appl. No.:
13/112132
Inventors:
Erich James Plondke - Austin TX, US
Lucian Codrescu - Austin TX, US
William C. Anderson - Austin TX, US
Lucian Codrescu - Austin TX, US
William C. Anderson - Austin TX, US
Assignee:
QUALCOMM INCORPORATED - San Diego CA
International Classification:
G06F 12/00, G06F 11/16, G06F 12/08
US Classification:
714 54, 711105, 711E12017, 714E11056, 711E12001
Abstract:
Systems and method for configuring a page-based memory device without pre-existing dedicated metadata. The method includes reading metadata from a metadata portion of a page of the memory device, and determining a characteristic of the page based on the metadata. The memory device may be configured as a cache. The metadata may include address tags, such that determining the characteristic may include determining if desired information is present in the page, and reading the desired information if it is determined to be present in the page. The metadata may also include error-correcting code (ECC), such that determining the characteristic may include detecting errors present in data stored in the page. The metadata may further include directory information, memory coherency information, or dirty/valid/lock information.