WILLIAM A JONES, MD
Urology at Eagle Rd, Meridian, ID

6901013, May 31, 2005

Jun 5, 2001

09/874894

William Jones - Boise ID, US
Wen Li - Boise ID, US
Mark R. Thomann - Boise ID, US
Timothy B. Cowles - Boise ID, US
Daniel R. Loughmiller - Boise ID, US

Micron Technology, Inc. - Boise ID

G11C007/00

365194, 365233

A method of monitoring the characteristics of a delay locked loop (DLL) in a memory device during a test mode is provided. The DLL generates an internal clock signal based on an external clock signal. The external and internal clock signals are normally synchronized. DLL constantly responds to variations in operating condition of the memory device to keep the external and internal clock synchronized. The method involves preventing the DLL from responding to a change in operating condition such as a change in the supply voltage of the memory device during a test mode.

6724670, Apr 20, 2004

Oct 21, 2002

10/277063

William F. Jones - Boise ID
Wen Li - Boise ID

Micron Technology, Inc. - Boise ID

G11C 700

365200, 3652257, 365235

A shared redundancy prefetch scheme to provide a reduced number of fuses. DDR SDRAMs allow burst addressing at various burst lengths. DDR SDRAMs generally implement LEFT and RIGHT segment column addressing. In DDR SDRAMs which implement redundant memory arrays, fuses may be used to provide access to the redundant columns. Because burst addressing may begin with a RIGHT segment address, two different columns may be accessed on the same clock cycle. By providing a compare scheme which implements separate compare logic for the lower bits of the LEFT and RIGHT segments and compares these bits to a common fuse set used for both the LEFT and RIGHT segments, the number of fuses in the redundant DDR SDRAM scheme can be reduced.

6819603, Nov 16, 2004

Aug 29, 2002

10/231512

William Jones - Boise ID
Wen Li - Boise ID

Micron Technology, Inc. - Boise ID

G11C 700

365194, 365233

A method of controlling a delay locked loop (DLL) in a memory device is provided. The DLL generates an internal clock signal based on an external clock signal. The DLL constantly responds to variations in operating condition of the memory device to keep the external and internal clock synchronized. The method involves preventing the DLL from responding to a change in operating condition such as a change in the supply voltage of the memory device during an operational mode of the memory device such as an active mode, a read mode, or a refresh mode.

7968916, Jun 28, 2011

Feb 19, 2010

12/709261

Jacob Robert Anderson - Meridian ID, US
William Jones - Boise ID, US

Micron Technology, Inc. - Boise ID

H01L 27/118

257203, 257272, 257777, 438106

Signals are routed to and from identical stacked integrated circuit dies by selectively coupling first and second bonding pads on each of the dies to respective circuits fabricated on the dies through respective transistors. The transistors connected to the first bonding pads of an upper die are made conductive while the transistors connected to the second bonding pads of the upper die are made non-conductive. The transistors connected to the second bonding pads of a lower die are made conductive while the transistors connected to the first bonding pads of the lower die are made non-conductive. The second bonding pads of the upper die are connected to the second bonding pads of the lower die through wafer interconnects extending through the upper die. Signals are routed to and from the circuits on the first and second dies through the first and second bonding pads, respectively.

2011023, Sep 29, 2011

Jun 8, 2011

13/156265

Jake Anderson - Meridian ID, US
William Jones - Boise ID, US

Micron Technology, Inc. - Boise ID

H01L 21/98

438109, 257E21705

Signals are routed to and from identical stacked integrated circuit dies by selectively coupling first and second bonding pads on each of the dies to respective circuits fabricated on the dies through respective transistors. The transistors connected to the first bonding pads of an upper die are made conductive while the transistors connected to the second bonding pads of the upper die are made non-conductive. The transistors connected to the second bonding pads of a lower die are made conductive while the transistors connected to the first bonding pads of the lower die are made non-conductive. The second bonding pads of the upper die are connected to the second bonding pads of the lower die through wafer interconnects extending through the upper die. Signals are routed to and from the circuits on the first and second dies through the first and second bonding pads, respectively.

7679198, Mar 16, 2010

May 4, 2007

11/800472

Jacob Robert Anderson - Meridian ID, US
William Jones - Boise ID, US

Micron Technology, Inc. - Boise ID

H01L 29/40

257777, 438598, 307115

Signals are routed to and from identical stacked integrated circuit dies by selectively coupling first and second bonding pads on each of the dies to respective circuits fabricated on the dies through respective transistors. The transistors connected to the first bonding pads of an upper die are made conductive while the transistors connected to the second bonding pads of the upper die are made non-conductive. The transistors connected to the second bonding pads of a lower die are made conductive while the transistors connected to the first bonding pads of the lower die are made non-conductive. The second bonding pads of the upper die are connected to the second bonding pads of the lower die through wafer interconnects extending through the upper die. Signals are routed to and from the circuits on the first and second dies through the first and second bonding pads, respectively.