William A Johnson, II
Engineers in Palo Alto, CA
License number
Colorado 18155
Issued Date
May 11, 1981
Renew Date
Jan 10, 1992
Expiration Date
Jan 10, 1992
Type
Professional Engineer
Address
Address
PO Box 2022, Palo Alto, CA 94309
Organization information
See more information about William A Johnson at bizstanding.comWILLIAM A. JOHNSON II, P.E., INC
PO Box 22, Palo Alto, CA 94309
Status:
Inactive
Registration:
Jan 22, 1993
State ID:
C1718949
Agent:
William A. Johnson Ii,Los Angeles, CA 90056 (Physical)
Professional information
Grounding A Pcb To An Enclosure Sub-Assembly Using A Grounding Spring
US Patent:
6065980, May 23, 2000
Filed:
Jun 29, 1998
Appl. No.:
9/106799
Inventors:
Sherman Leung - San Jose CA
William Blake Johnson - Palo Alto CA
Victor Vigdorchik - Belmont CA
William Blake Johnson - Palo Alto CA
Victor Vigdorchik - Belmont CA
Assignee:
Cisco Technology, Inc. - San Jose CA
International Classification:
H01R 466
US Classification:
439 92
Abstract:
Grounding a PCB to an enclosure sub-assembly is accomplished using a specially designed spring. The spring contains a base portion, an inclined portion and a head portion. Holes are provided in the base portion of the spring to allow for soldering to make a much stronger bond, reducing the chance of separation. A tab is provided on the top portion to reduce snagging nearby objects during installation. Notches are placed between the head portion and flaps connected to he head portion in order to reduce tearing that may occur during manufacture. The spring may then be used with a specially designed enclosure sub-assembly having a drawn feature, the drawn feature engaging the spring and compressing it, allowing grounding to occur. The drawn feature allows for the single spring design to be used in a wide variety of products.
Electrically Alterable Read-Mostly Memory
US Patent:
4266283, May 5, 1981
Filed:
Feb 16, 1979
Appl. No.:
6/012670
Inventors:
George Perlegos - Cupertino CA
William S. Johnson - Palo Alto CA
William S. Johnson - Palo Alto CA
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
B11C 1140
US Classification:
365104
Abstract:
An electrically alterable read-mostly MOS memory (commonly referred to as E. sup. 2 PROM) employing floating gate memory devices is described. Each word stored in memory may be separately accessed for reading and writing. The memory array is arranged with additional lines and selection means to prevent the high-level programming signals from the X-decoders from programming all the floating gate devices along a selected X-line. A high voltage circuit is described which permits the handling of potentials greater than the grounded gate breakdown voltage associated with the shallow junction devices used in the memory. A unique sensing amplifier is also disclosed which detects low currents at high speeds.
Electrically Programmable And Erasable Mos Floating Gate Memory Device Employing Tunneling And Method Of Fabricating Same
US Patent:
4203158, May 13, 1980
Filed:
Dec 15, 1978
Appl. No.:
5/969819
Inventors:
Dov Frohman-Bentchkowsky - Haifa, IL
Jerry Mar - Sunnyvale CA
George Perlegos - Cupertino CA
William S. Johnson - Palo Alto CA
Jerry Mar - Sunnyvale CA
George Perlegos - Cupertino CA
William S. Johnson - Palo Alto CA
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G11C 1140
US Classification:
365185
Abstract:
An electrically programmable and electrically erasable MOS memory device suitable for high density integrated circuit memories is disclosed. Carriers are tunneled between a floating conductive gate and a doped region in the substrate to program and erase the device. A minimum area of thin oxide (70 A-200 A) is used to separate this doped region from the floating gate. In one embodiment, a second layer of polysilicon is used to protect the thin oxide region during certain processing steps.