WEI WU
Pilots at Cornell Rd, Beaverton, OR
License number
Oregon A5250014
Issued Date
Jun 2015
Expiration Date
Jun 2016
Category
Airmen
Type
Authorized Aircraft Instructor
Address
Address
3565 NE Cornell Rd, Beaverton, OR 97124
Personal information
See more information about WEI WU at radaris.comName
Address
Phone
5975 Volcano St SE, Salem, OR 97306
3653 NW Goldfinch Dr, Corvallis, OR 97330
3952 SE 100Th Ave, Portland, OR 97266
5936 Tibbetts St, Portland, OR 97206
13624 Davis St, Portland, OR 97230
Professional information
Performing Multi-Bit Error Correction On A Cache Line
US Patent:
8245111, Aug 14, 2012
Filed:
Dec 9, 2008
Appl. No.:
12/331255
Inventors:
Zeshan A. Chishti - Hillsboro OR, US
Alaa R. Alameldeen - Aloha OR, US
Chris Wilkerson - Portland OR, US
Wei Wu - Hillsboro OR, US
Dinesh Somasekhar - Portland OR, US
Muhammad Khellah - Tigard OR, US
Shih-Lien Lu - Portland OR, US
Alaa R. Alameldeen - Aloha OR, US
Chris Wilkerson - Portland OR, US
Wei Wu - Hillsboro OR, US
Dinesh Somasekhar - Portland OR, US
Muhammad Khellah - Tigard OR, US
Shih-Lien Lu - Portland OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 11/00
US Classification:
714766, 714752
Abstract:
A processor may comprise a cache, which may be divided into a first and second section while the processor operates in a low-power mode. A cache line of the first section may be fragmented into segments. A first encoder may generate first data bits and check bits while encoding a first portion of a data stream and a second encoder may, separately, generate second data bits and check bits while encoding a second portion of the data stream. The first data bits may be stored in a first segment of the first section and the check bits in a first portion of the second section that is associated with the first segment. The first decoder may correct errors in multiple bit positions within the first data bits using the check bits stored in the first portion and the second decoder may, separately, decode the second data bits using the second set of check bits.
Providing Metadata In A Translation Lookaside Buffer (Tlb)
US Patent:
2012029, Nov 22, 2012
Filed:
Jul 17, 2012
Appl. No.:
13/550817
Inventors:
David Champagne - Princeton NJ, US
Abhishek Tiwari - Urbana IL, US
Wei Wu - Hillsboro OR, US
Christopher J. Hughes - San Jose CA, US
Sanjeev Kumar - San Jose CA, US
Shih-Lien Lu - Portland OR, US
Abhishek Tiwari - Urbana IL, US
Wei Wu - Hillsboro OR, US
Christopher J. Hughes - San Jose CA, US
Sanjeev Kumar - San Jose CA, US
Shih-Lien Lu - Portland OR, US
International Classification:
G06F 12/10
US Classification:
711207, 711E12061
Abstract:
In one embodiment, the present invention includes a translation lookaside buffer (TLB) to store entries each having a translation portion to store a virtual address (VA)-to-physical address (PA) translation and a second portion to store bits for a memory page associated with the VA-to-PA translation, where the bits indicate attributes of information in the memory page. Other embodiments are described and claimed.
Providing Metadata In A Translation Lookaside Buffer (Tlb)
US Patent:
8250334, Aug 21, 2012
Filed:
May 2, 2011
Appl. No.:
13/098733
Inventors:
David Champagne - Princeton NJ, US
Abhishek Tiwari - Urbana IL, US
Wei Wu - Hillsboro OR, US
Christopher J. Hughes - San Jose CA, US
Sanjeev Kumar - San Jose CA, US
Shih-Lien Lu - Portland OR, US
Abhishek Tiwari - Urbana IL, US
Wei Wu - Hillsboro OR, US
Christopher J. Hughes - San Jose CA, US
Sanjeev Kumar - San Jose CA, US
Shih-Lien Lu - Portland OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 12/10
US Classification:
711207, 711 3, 711108, 711144, 711202, 711206
Abstract:
In one embodiment, the present invention includes a translation lookaside buffer (TLB) to store entries each having a translation portion to store a virtual address (VA)-to-physical address (PA) translation and a second portion to store bits for a memory page associated with the VA-to-PA translation, where the bits indicate attributes of information in the memory page. Other embodiments are described and claimed.
Providing Metadata In A Translation Lookaside Buffer (Tlb)
US Patent:
7941631, May 10, 2011
Filed:
Dec 28, 2007
Appl. No.:
12/005892
Inventors:
David Champagne - Princeton NJ, US
Abhishek Tiwari - Urbana IL, US
Wei Wu - Hillsboro OR, US
Christopher J. Hughes - San Jose CA, US
Sanjeev Kumar - San Jose CA, US
Shih-Lien Lu - Portland OR, US
Abhishek Tiwari - Urbana IL, US
Wei Wu - Hillsboro OR, US
Christopher J. Hughes - San Jose CA, US
Sanjeev Kumar - San Jose CA, US
Shih-Lien Lu - Portland OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 12/10
US Classification:
711207, 711 3, 711108, 711144, 711202, 711206
Abstract:
In one embodiment, the present invention includes a translation lookaside buffer (TLB) to store entries each having a translation portion to store a virtual address (VA)-to-physical address (PA) translation and a second portion to store bits for a memory page associated with the VA-to-PA translation, where the bits indicate attributes of information in the memory page. Other embodiments are described and claimed.