WAYNE S SMITH
Accountancy in Portland, OR

License number
Massachusetts 18922
Issued Date
Feb 26, 1998
Expiration Date
Jun 30, 2007
Type
Certified Public Accountant
Address
Address
Portland, OR 97214
LicenseFiles verified this license of Nov 24, 2016 at the Mass.gov - Consumer Affairs and Business Regulation.

Professional information

Wayne Smith Photo 1

Managing Member At Dragon Curve Capital Llc
Position:
Managing Member at Dragon Curve Capital LLC
Location:
Portland, Oregon Area
Industry:
Financial Services
Work:
Dragon Curve Capital LLC since Jan 2010 - Managing Member Touchstone Investment Managers, LLC Feb 2000 - Dec 2009 - COO Mikles Miller Management Jun 1998 - Jan 2000 - Analyst PricewaterhouseCoopers 1996 - 1998 - Senior Analyst
Education:
Northeastern University 1994 - 1996
MBS/MS, Accounting Harvard University 1989 - 1993

Wayne Smith Photo 2

Information Assurance Manager At Dod
Position:
Information Assurance Manager at DoD (Sole Proprietorship)
Location:
Portland, Oregon Area
Industry:
Information Technology and Services
Work:
DoD - Information Assurance Manager

Wayne Smith Photo 3

Cache Access Controller And Method For Permitting Caching Of Information In Selected Cache Lines

US Patent:
5572700, Nov 5, 1996
Filed:
Apr 30, 1993
Appl. No.:
8/055962
Inventors:
Kirk I. Hays - Hillsboro OR
Wayne D. Smith - Portland OR
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 1200
US Classification:
395466
Abstract:
A cache access controller and method for controlling access to a cache memory are implemented in a computer system having a processor for performing memory access operations specifying an address in main memory, and a cache memory comprised of a number of cache lines. The cache access controller includes a control circuit which produces a number of access values in response to the address, each access value being associated with a cache line and having a true or a false state. The controller also includes an access logic circuit which permits the caching of information associated with the address at a cache line if the access value associated with that cache line is true. An operator register and a parameter register associated with a cache line may be used in conjunction with the address to determine the access value for that cache line using arithmetic, logical, or a combination of arithmetic and logical, functions.

Wayne Smith Photo 4

Server Administrator Lead At Phoenix Health Systems
Position:
Server Administrator Lead at Phoenix Health Systems
Location:
Portland, Oregon Area
Industry:
Hospital & Health Care
Work:
Phoenix Health Systems - Server Administrator Lead
Education:
Oregon State University 1992 - 2004

Wayne Smith Photo 5

Wayne Smith
Location:
Portland, Oregon Area
Industry:
Hospital & Health Care

Wayne Smith Photo 6

Translation Lookaside Buffer (Tlb) Arrangement Wherein The Tlb Contents Retained For A Task As Swapped Out And Reloaded When A Task Is Rescheduled

US Patent:
6356989, Mar 12, 2002
Filed:
Dec 21, 1992
Appl. No.:
07/993783
Inventors:
Kirk Hays - Hillsboro OR
Wayne D. Smith - Portland OR
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 1210
US Classification:
711205
Abstract:
An improved method and apparatus for utilizing Translation Lookaside Buffers (TLB) for maintaining page tables in a paging unit on a computer system. TLB contents for executing tasks are retained when the task is swapped out. The contents are then reloaded into the TLB when the task is again scheduled for execution. Spare memory cycles are utilized to transfer outgoing TLB data into memory, and incoming TLB data for a next scheduled task from memory.

Wayne Smith Photo 7

Method And Apparatus For Counting Instruction Types Using Bit Masks And A Programmable Bit Map

US Patent:
5388233, Feb 7, 1995
Filed:
Apr 30, 1993
Appl. No.:
8/056075
Inventors:
Kirk I. Hays - Hillsboro OR
Wayne D. Smith - Portland OR
Assignee:
Intel Corporation - Santal Clara CA
International Classification:
G06F 930
US Classification:
395375
Abstract:
A counter for counting instructions is implemented in a computer system having a processor in which instructions are fetched for potential execution. Each instruction is characterized by at least one instruction attribute. The counter includes at least one bit map register for storing a bit map. Each map bit position in the bit map represents a particular instruction attribute. Map bits at predetermined map bit positions are set. A bit mask register stores a bit mask corresponding to a fetched instruction. Each mask bit position in the bit mask represents a particular instruction attribute. A mask bit at a mask bit position is set if the mask bit position represents an instruction attribute of the fetched instruction. Logic circuitry increments a count value associated with a bit map based upon a comparison of the bit map with the bit mask.

Wayne Smith Photo 8

Register Stacking In A Computer System

US Patent:
5640582, Jun 17, 1997
Filed:
Aug 17, 1994
Appl. No.:
8/291744
Inventors:
Kirk I. Hays - Hillsboro OR
Wayne D. Smith - Portland OR
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 900
US Classification:
395800
Abstract:
A computer system provides an expanded register set by employing transparent register stacks for each general purpose register. Each general purpose register and its corresponding set of auxiliary registers form a register stack. No register identification bits are required in processor instructions to reference auxiliary registers. A register set select storage area is a programmable register provided for the storage of a value that identifies the currently active register level. The register set select storage area is loaded using two additional processor instructions provided as part of the present invention. A register set switch is used for selecting a data path to the register level specified by the register set select storage area. A PUSHREG instruction is used to push the register stack pointer down one level. A POPREG instruction is used to move the register stack pointer up one register level.

Wayne Smith Photo 9

Translation Lookaside Buffer (Tlb) Arrangement Wherein The Tlb Contents Are Retained From Task When It Is Swapped Out And Reloaded When The Task Is Rescheduled

US Patent:
5640533, Jun 17, 1997
Filed:
Dec 13, 1995
Appl. No.:
8/571455
Inventors:
Kirk Hays - Hillsboro OR
Wayne D. Smith - Portland OR
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 1212
US Classification:
395460
Abstract:
An improved method and apparatus for utilizing Translation Lookaside Buffers (TLB) for maintaining page tables in a paging unit on a computer system. TLB contents for executing tasks are retained when the task is swapped out. The contents are then reloaded into the TLB when the task is again scheduled for execution. Spare memory cycles are utilized to transfer outgoing TLB data into memory, and incoming TLB data for a next scheduled task from memory.

Wayne Smith Photo 10

Method And An Apparatus For Minimizing Perturbation While Monitoring Parallel Applications

US Patent:
6021457, Feb 1, 2000
Filed:
Jul 15, 1997
Appl. No.:
8/893129
Inventors:
David W. Archer - Beaverton OR
Don Breazeal - Portland OR
Suresh Chittor - Beaverton OR
Richard J. Greco - West Linn OR
Wayne D. Smith - Portland OR
Jim Sutton - Portland OR
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 104
US Classification:
710260
Abstract:
A multiprocessor system and method for minimizing perturbations while monitoring parallel applications. Perturbations due to monitoring the application are minimized by synchronizing all the nodes within the system to a very accurate global time clock such that all the nodes running the application stop and restart running the application at the same time. Within the time period bounded by the stop and restart time, all the performance monitoring data is transferred from performance monitoring data buffers to a secondary memory.

Accountancy licenses in Massachusetts