WARD DOUGLAS PARKINSON
Pilots at Bluestem Ln, Boise, ID

6545907, Apr 8, 2003

Oct 30, 2001

10/021469

Tyler A. Lowrey - San Jose CA
Ward D. Parkinson - Boise ID
Manzur Gill - Cupertino CA

Ovonyx, Inc. - Boise ID

G11C 1100

365163, 36518901

A technique includes, in response to a request to write data to memory cells of a phase change memory device, placing the memory cells in a state that is shared in common among the memory cells. Also, in response to this request, the data is written to the memory cells.

4527185, Jul 2, 1985

Jan 6, 1984

6/568291

Elliott Philofsky - Myrtle Beach SC
Ward Parkinson - Boise ID
Dennis Wilson - Boise ID

AVX Corporation - Great Neck NY

H01L 2314, H01L 2502, H01L 2348

357 70

The present invention relates to an integrated circuit device particularly of the type carrying multiple memory circuits or the like. The device incorporates a lead frame of the sort which includes an elongate metallic web and is characterized by the lead frame providing an integral seat or platform whereon is mounted a capacitor device which is connected or adapted to be connected in shunting relation of the power supply inputs to the integrated circuit device, whereby the capacitor provides a convenient mounting platform for the circuit bearing elements and also assures minimal lead lengths between the capacitor and the power supply inputs of the circuit bearing chip. Due to the shortness of such lead lengths and consequent reduction of the inductance reactance of the power supply circuit, efficient dampening of switching transients is achieved with the use of capacitors of much smaller values, in less area than heretofore required in external dampening applications.

2012028, Nov 8, 2012

Jul 14, 2012

13/549436

Ward Parkinson - Boise ID, US

G11C 8/10, G11C 11/21

365148, 36523006, 365163

A thin-film memory may include a thin-film transistor-free address decoder in conjunction with thin-film memory elements to yield an all-thin-film memory. Such a thin-film memory excludes all single-crystal electronic devices and may be formed, for example, on a low-cost substrate, such as fiberglass, glass or ceramic. The memory may be configured for operation with an external memory controller.

8441836, May 14, 2013

Sep 17, 2010

12/884413

Ward Parkinson - Boise ID, US
Thomas Trent - Nashua NH, US

Ovonyx, Inc. - Sterling Heights MI

G11C 11/00

365148, 365158

An addressing scheme for non-volatile memory arrays having short circuit defects that manages the demand for error correction. The scheme generally avoids simultaneous active driving of the row line and column line of the selected cell during write. Instead, only a single row or column line is actively driven at any one time and all other array lines are left floating. In addition, the number of memory cells accessed from a given row or column during a fetch may be limited. The benefits of the scheme include preventing short circuits from drawing excess currents through the array and limiting the frequency of read or write failures caused by short circuits to a manageable number. In one embodiment, the scheme maintains the demand for error correction to within the error correction capability of a flash controller. Exemplary embodiments include phase-change memory arrays.

2006005, Mar 16, 2006

Sep 10, 2004

10/938705

Ward Parkinson - Boise ID, US
Manzur Gill - Cupertino CA, US

G11C 11/00, G11C 5/06

365163000, 365063000

A phase change memory may be utilized to replace NAND flash memory in combination with a buffer such as a static random access memory and/or a dynamic random access memory. Because the phase change memory may have sufficiently low cost, it may replace low cost NAND flash and because the phase change memory has sufficiently high performance, it can also replace the dynamic random access or static random access buffer memory sometimes packaged with the NAND flash memory. Thus, a relatively low cost, high performance solution is achieved in a relatively small package size in some embodiments.

5555429, Sep 10, 1996

May 8, 1995

8/437447

Ward D. Parkinson - Boise ID
William K. Waller - Boise ID
Mirmajid Seyyedy - Boise ID

Micron Technology, Inc. - Boise ID

G06F 1516

395800

Presented is an integrated circuit chip including a random access memory (RAM) array, serial access memory (SAM), an arithmetic logic unit, a bidirectional shift register, and masking circuitry. The arithmetic logic unit, SAM, shift register, and masking circuitry are all as wide as one side of the RAM array, and are all communicable with each other via data transfer means. This allows wide word processing, user configurable for parallel processing. Bits masked by the masking circuitry are selectable by data in the bidirectional shift register, providing shiftable masking means. Random access and serial access are done through separate ports. The bidirectional shift register is optionally serially accessible. Methods of use are also presented.

4924442, May 8, 1990

Sep 30, 1988

7/252494

Zhitong Chen - Boise ID
Gary M. Johnson - Boise ID
Ward D. Parkinson - Boise ID
Wen-Foo Chern - Boise ID
Tyler A. Lowrey - Boise ID
Thomas M. Trent - Boise ID

Micron Technology, Inc. - Boise ID

G11C 700, H03K 508

36518911

A voltage sensing circuit is used to rapidly pull up a high potential node of a reference array to a value of a high potential source reduced by a threshold voltage (V. sub. CC -V. sub. T). During an enable cycle, the high potential node is precharged to a potential of V. sub. CC -V. sub. T, which turns on a transistor gated to the V. sub. CC potential. This pulls the high potential node as rapidly as possible to a high level in order to speed up the sensing process. A potential maintenance circuit provides sufficient current from the high potential source to maintain a desired potential at the high potential node.

7466584, Dec 16, 2008

Jan 2, 2008

12/006391

Ward Parkinson - Boise ID, US
John Peters - San Jose CA, US

Ovonyx, Inc. - Rochester Hills MI

G11C 11/00

365163, 365148

An electronic system includes a control device in combination with an ovonic threshold switch (OTS). The control device, which may be a field effect transistor, a bipolar junction transistor, or a three-terminal ovonic threshold switch, for example, is configured to trigger the OTS. The OTS, a high current-density device, may be configured to drive greater loads than the control device itself would be capable of driving.

7280390, Oct 9, 2007

Apr 14, 2005

11/105829

Sergey A. Kostylev - Bloomfield Hills MI, US
Tyler Arthur Lowrey - West Augusta VA, US
Wolodymyr Czubatyj - Warren MI, US
Ward D. Parkinson - Boise ID, US

Ovonyx, Inc. - Rochester Hills MI

G11C 11/00

365163, 365113, 365148

A phase change memory may be read so as to reduce the likelihood of a read disturb. A read disturb may occur, for example, when a reset device is raised to a voltage, which causes its threshold device to trigger. The triggering of the threshold device produces a displacement current which may convert a reset device to a set device. By ensuring that the reset cell never reaches a voltage that would result in triggering of the threshold device, read disturbs may be reduced.

7271403, Sep 18, 2007

Dec 13, 2002

10/319183

Ilya Karpov - Santa Clara CA, US
Ward Parkinson - Boise ID, US
Sean Lee - Sunnyvale CA, US

Intel Corporation - Santa Clara CA

H01L 47/00

257 2, 257 73, 257 3, 257 4, 257 5

A phase change memory may be made using an isolation diode in the form of a Schottky diode between a memory cell and a word line. The use of Schottky diode isolation devices may make the memory more scaleable in some embodiments.