VINH AI NGUYEN
Nail Technician in San Jose, CA

License number
Virginia 1206006843
Issued Date
Apr 17, 1996
Expiration Date
Apr 30, 2000
Category
Nail Technician License
Type
Nail Technician
Address
Address
San Jose, CA

Personal information

See more information about VINH AI NGUYEN at radaris.com
Name
Address
Phone
Vinh Van Nguyen
4776 El Cajon Blvd STE 101, San Diego, CA 92115
Vinh Van Nguyen
46 El Morro, Rcho Sta Marg, CA 92688
Vinh Van Nguyen
4709 E Bradford Ave, Orange, CA 92867
Vinh Van Nguyen
4725 W 1St St, Santa Ana, CA 92703
(714) 531-7476
Vinh Van Nguyen
4950 Scarlett Way, San Jose, CA 95111

Professional information

See more information about VINH AI NGUYEN at trustoria.com
Vinh Nguyen Photo 1
Vinh Nguyen - San Jose, CA

Vinh Nguyen - San Jose, CA

Work:
United States Army
Human Resources Specialist/ Computer Specialist
Holiday Cleaners Inc
Payroll Specialist/Office manger
Holiday Cleaners Inc - Cupertino, CA
Desktop Support
Heald College - Salinas, CA
Computer Technology Instructor
EBAY Incorporated - San Jose, CA
IT Desktop/Network Support (Intern)
Education:
University of California - Santa Cruz, CA
Bachelor in Computer Engineering
Realty College - San Jose, CA
Certificate in General Accounting


Vinh Quy Nguyen Photo 2
Vinh Quy Nguyen, San Jose CA

Vinh Quy Nguyen, San Jose CA

Specialties:
Internist
Address:
200 Jose Figueres Ave, San Jose, CA 95116
Education:
Creighton University, School of Medicine - Doctor of Medicine
University of Louisville Hospital - Residency - Internal Medicine
Board certifications:
American Board of Internal Medicine Certification in Internal Medicine


Vinh Nguyen Photo 3
Vinh Nguyen - San Jose, CA

Vinh Nguyen - San Jose, CA

Work:
Intertek Pharmaceutical Services - San Diego, CA
Associate Project Coordinator
Human Earth Rights Organization - San Diego, CA
President
Genovo - Carlsbad, CA
Research Associate
University of California, San Diego - La Jolla, CA
Lab Volunteer
Education:
University of California at San Diego - La Jolla, CA
B.S. in Molecular Biology


Vinh Nguyen Photo 4
Vinh Nguyen - San Jose, CA

Vinh Nguyen - San Jose, CA

Work:
INTEVAC
Positioning as electro/mechanical assembler, vacuum tester
LAM RESEARCH CORP
Positioned as electro/ mechanical assembler, vacuum tester
Education:
vietnam
High school diploma


Vinh Nguyen Photo 5
Vinh Nguyen - San Jose, CA

Vinh Nguyen - San Jose, CA

Work:
Vertical Test - San Jose, CA
Sr. Test Technician
ST Micro. - Carolltons, TX
Sr. Test Technician
SV Probe, Inc. - San Jose, CA
Probe Cards Specialist.
Avantek-HP - Santa Clara, CA
Test Technician.
N/A
N/A
N/A
N/A
N/A
N/A
Education:
Mission College
Science
Skills:
Solidworks, AutoCad, Exell, MS


Vinh Nguyen Photo 6
Vinh Nguyen, San Jose CA

Vinh Nguyen, San Jose CA

Work:
Sharp Rees-Stealy Med Group
175 N Jackson Ave, San Jose, CA 95116 Sharp Rees-Stealy Med Group
5525 Grossmont Center Dr, La Mesa, CA 91942


Vinh Nguyen Photo 7
Contact Probe Pin For Wafer Probing Apparatus

Contact Probe Pin For Wafer Probing Apparatus

US Patent:
6507207, Jan 14, 2003
Filed:
Feb 20, 2001
Appl. No.:
09/789600
Inventors:
Vinh T. Nguyen - San Jose CA 95123
International Classification:
G01R 3102
US Classification:
324761, 324754
Abstract:
An improved contact probe pin for wafer probing apparatus including an elongated metal conductor having a connector (or proximal) end, a center or medial section coated with an elastic material, and a contact pad engaging tip end. At least a portion of the center section of the probe pin is coated with a poorly conductive, but highly elastic material so as to enhance its flex characteristics. The coating may uniformly cover a portion of the center section of the probe pin or it may take on a predetermined pattern or shape. The coating may also unevenly cover a portion of the center section of the probe pin. The coating is selected such that it augments or enhances the resiliency of the pin and causes it to have a predetermined stress-strain profile with vertical (or Z-axis) displacement, and thus enables it to have predetermined probe pin tip contact force characteristics.


Vinh Nguyen Photo 8
Vinh Nguyen, San Jose CA

Vinh Nguyen, San Jose CA

Work:
Century 21
San Jose
(408) 927-4080


Vinh Nguyen Photo 9
Multilayer Circuit Device Having Electrically Isolated Tightly Spaced Electrical Current Carrying Traces

Multilayer Circuit Device Having Electrically Isolated Tightly Spaced Electrical Current Carrying Traces

US Patent:
8338712, Dec 25, 2012
Filed:
Dec 15, 2010
Appl. No.:
12/969478
Inventors:
Vinh T. Nguyen - San Jose CA, US
Claude A. S. Hamrick - Lincoln CA, US
International Classification:
H05K 1/00
US Classification:
174250
Abstract:
A multilayer circuit device having electrically isolated tightly spaced electrical current carrying traces and including a first nonconductive substrate having a first conductive material affixed to a first side thereof to form a first ground plane, a plurality of elongated first conductive traces formed on a second side of the first non-conductive substrate and having transverse widths of 50 microns or less and rising above the upper surface of the first substrate to a height equal to or greater than the widths thereof such that a transverse cross section of the first conductive traces has a height-to-width ratio equal to or exceeding 1, adjacent ones of the first traces being separated from each other by first elongated spaces, the first conductive traces being variously useful as ground lines, signal lines and/or power lines.


Vinh Nguyen Photo 10
Process For Making A Multilayer Circuit Board

Process For Making A Multilayer Circuit Board

US Patent:
7874065, Jan 25, 2011
Filed:
Oct 31, 2008
Appl. No.:
12/263416
Inventors:
Vinh T. Nguyen - San Jose CA, US
Claude A. S. Hamrick - San Jose CA, US
International Classification:
H05K 3/36
US Classification:
29830, 29840, 29846, 29852, 427 971, 427 972
Abstract:
A process for making a multi-layered circuit board having electrical current traces includes providing a substrate having a 1layer of conductive material to form a ground plane, plurality of metallic 1traces on a 2side of the substrate having widths of approximately 25 microns or less, developing 1ribs of photoresist forming 1walls rising above upper surface of an adjacent seed layer trace, depositing 1conductive signal traces having a thickness exceeding 25 microns into channels and over seed layer traces and stripping the ribs to leave 1conductive traces having a height-to-transverse ratio exceeding 1.