VAN NGUYEN, D.D.S.
Dentist at Park Blvd, Plano, TX

5732236, Mar 24, 1998

May 28, 1993

8/068819

Van Minh Nguyen - Plano TX
Patrick W. Bosshart - Plano TX

Texas Instruments Incorporated - Dallas TX

G06F 1206

395405

A DRAM controller (18) for controlling access to a system memory (11) is provided. Prioritizer circuit (38) causes a first plurality of buffers (42) to pass an address signal (46) for a first requesting circuit to a primary address bus (48) and a second plurality of buffers (44) to pass an address signal (46) for a next requesting circuit to a secondary address bus (50). The pages requested on primary address bus (48) and secondary address bus (50) are compared with the active page of each memory bank (11) stored in registers (52), (54), (56), and (58) by first and second plurality of comparators (60) and (70) to determine if the pages are active. The output of each of the first and second plurality of comparators (60) and (70) is coupled to a corresponding bank controller in a plurality of bank controllers (84) to produce control signals on control lines (26). A first bank decoder (80) enables an appropriate one of the plurality of bank controllers (84) to precharge an appropriate control line (26) corresponding to input from first plurality of comparators (60). The first requesting circuit signals DRAM controller (18) through a multiplexer (94) that the first requesting circuit is ready to finish accessing system memory (11) thereby allowing second bank decoder (82) to enable an appropriate one of the plurality of bank controllers (84) to precharge an appropriate control line (26) corresponding to input from second plurality of comparators (70).

5583893, Dec 10, 1996

Aug 19, 1994

8/293762

Van M. Nguyen - Plano TX

Texas Instruments Incorporated - Dallas TX

H04L 700

375357

A method and apparatus are disclosed for safely suspending and resuming operation of an electronic device. The method comprises the step of generating a DUT-NXCLK-IN in response to a first NXCLK-IN to drive an electronic device 12 DUT-CLK-OUT is received from the device 12 wherein DUT-CLK-OUT comprises DUT-NXCLK-IN divided by a first value. ESYNER-CLK-OUT is generated by dividing NXCLK-IN by the first value. ESYNER-CLK-OUT is synchronized to signal-DUT-CLK-OUT. DUT-NXCLK-IN is disabled in response to a test grant signal TEST-GRANT when the ESYNER-CLK-OUT is in a predetermined one of a plurality of states. The disabled DUT-NXCLK-IN is re-enabled in response to the test grant signal TEST-GRANT when ESYNER-CLK-OUT is in the state immediately following the predetermined one of a plurality of states.

5781718, Jul 14, 1998

Aug 19, 1994

8/293535

Van Minh Nguyen - Plano TX

Texas Instruments Incorporated - Dallas TX

G06F 1100

39518309

A method and apparatus are disclosed for generating modular test pattern sets for production testing of a digital circuit. The method comprises the steps of enabling a pattern generator (16) and executing a functional simulation on a functional simulator (18) until a first time mark. The pattern generator (16) is disabled and the state of the registers in the digital circuit (52) are captured using scanning circuitry in the circuit (52). The captured state is stored in a memory (68) external to the digital circuit (52). The pattern generator (16) is then re-enabled and the registers are reloaded from the memory (68) using the scanning circuitry of the circuit (52). The functional simulation is resumed until a second time mark. Whenever the pattern generator (16) is enabled, a pattern is stored on a storage medium (20) in response to a clock controlling the circuit (52) wherein each pattern represents the electrical state of the inputs and outputs of the circuit (52) during a particular clock cycle.