MR. TUAN VAN PHAN, MD
Marriage and Family Therapists at Lexann Ave, San Jose, CA

7536611, May 19, 2009

Nov 3, 2003

10/700177

Mukesh K. Puri - Fremont CA, US
Ghasi R. Agrawal - Sunnyvale CA, US
Tuan L. Phan - San Jose CA, US

LST Corporation - Milpitas CA

G11C 29/00

714710

A BISR scheme which provides for on-chip assessment of the amount of repair on a given memory and for the flagging of any device as a fail when the device exceeds a pre-determined limit. Preferably, a counter is built and loaded through a test pattern during production testing, and the counter establishes the threshold for pass/fail criteria. The BISR is configured to load a repair solution and then test the memories for any additional failures and if there are any, repair them (provided enough redundant elements are available). In addition, a reliability controller for BISR designs can be provided, where the reliability controller contains a register set and a number of counters at the chip-level which can be loaded through a test pattern during production tests, where one of the counters contains the number of memories to be allowed for repair.

6651202, Nov 18, 2003

Mar 8, 2001

09/802198

Tuan L. Phan - San Jose CA

LSI Logic Corporation - Milpitas CA

G01R 3128

714733, 714735

An integrated circuit includes built-in self test (BIST) and built-in self repair (BISR) circuitry, a fuse array capable of storing information related to defective memory locations identified during the manufacturing process. During manufacture, the integrity of the embedded memory of the integrated circuit is tested under a variety of operating conditions via the BIST/BISR circuitry. The repair solutions derived from these tests are stored and compiled in automated test equipment. If the repair solutions indicate that the embedded memory is repairable, the on-chip fuse array of the integrated circuit is programmed with information indicative of all of the detected defective memory locations. The built-in self repair circuitry of the integrated circuit is not executed upon power up. Instead, the repair information stored in the fuse array is provided to address remap circuitry within the BISR circuit.

6505313, Jan 7, 2003

Dec 17, 1999

09/466389

Tuan Phan - San Jose CA
William Schwarz - San Jose CA

LSI Logic Corporation - Milpitas CA

G11C 2900

714718, 714733

A memory device configured to detect changes in fault patterns is disclosed. In one embodiment, the memory device includes a memory array, a built-in self-test (BIST) unit, and a built-in self-repair (BISR) unit. The BIST unit runs test patterns on the memory array to identify faulty locations in the array. A comparator within the BIST or external to the BIST compares the actual output of the memory array to the expected output, and asserts an error signal whenever a mismatch occurs. The BISR unit intercepts addresses directed to the memory array, and operates on the addresses in three distinct phases. During a training phase, the BISR unit stores the intercepted addresses when the error signal is asserted. During the normal operation phase, the BISR unit compares all intercepted addresses to stored addresses and redirects a corresponding memory access if any intercepted address matches a stored address. During a verification phase, the BISR unit compares intercepted addresses designated by assertions of the error signal to the addresses previously stored in the training phase.

6367042, Apr 2, 2002

Dec 11, 1998

09/209996

Tuan L. Phan - San Jose CA
V. Swamy Irrinki - Milpitas CA

LSI Logic Corporation - Milpitas CA

G01R 3128

714733

A method for improving the fault coverage of manufacturing tests for integrated circuits having structures such as embedded memories. In the disclosed embodiment of the invention, the integrated circuit die of a semiconductor wafer are provided with a fuse array or other circuitry capable of storing an identification number. The integrated circuit die also include an embedded memory or similar circuit and built-in self-test (BIST) and built-in self-test (BISR) circuitry. At a point early in the manufacturing test process, the fuse array of each integrated circuit die is encoded with an identification number to differentiate the die from other die of the wafer or wafer lot. The integrity of the embedded memory of each integrated circuit die is then tested at the wafer level under a variety of operating conditions via the BIST and BISR circuitry. The results of these tests are stored in ATE and associated with a particular integrated circuit die via the identification number of the die. The manufacturing test process then continues for the packaged integrated circuits.

5903505, May 11, 1999

May 19, 1997

8/858271

Thomas R. Wik - Livermore CA
Tuan Phan - San Jose CA
Thien Trieu - Fremont CA

LSI Logic Corporation - Milpitas CA

G11C7/00

365222

A method for testing refresh operations of a memory array wherein subthreshold leakage current may be set to near worst-case conditions. The memory array includes a first row of memory cells having a first memory cell configured to store a first memory value, and a second row of memory cells having a second memory cell configured to store a second memory value. The method comprises storing a logic high value to the first memory cell as the first memory value, followed by storing a logic low value to the second memory cell as the second memory value. The method further comprises repeatedly driving a write bit line coupled to both the first and second memory cells at a logic low level for a period of a time equal to a refresh interval corresponding to the first memory cell. Additionally, the method includes subsequently reading the first memory value from the first memory cell. Finally, the method includes indicating that the first memory cell is operating correctly if the first memory value is still equal to a logic high value, or indicating that the first memory value is malfunctioning if the first memory value is equal to a logic low value.

6227637, May 8, 2001

May 14, 1998

9/078746

Tuan Phan - San Jose CA

LSI Logic Corporation - Milpitas CA

H01H 3776

325525

An information circuit in a semiconductor device suitable for encoding and retrieving a bit of information. The information circuit includes an input circuit and an output circuit. The input circuit includes an input node coupled to an input terminal of a transistor. The output circuit includes a load device, a fuse circuit, and first and second output terminals of the transistor all coupled in series between a power supply terminal and a ground terminal. The impedance of said fuse circuit is preferably alterable between an initial impedance and an altered impedance. An output node of said information circuit is coupled to said output circuit. The information circuit is configured such that the output node voltage is indicative of said impedance of said fuse circuit when said input node is biased to a "read" state, said power supply terminal is biased to a power supply voltage, and said ground terminal is grounded.

6067262, May 23, 2000

Dec 11, 1998

9/209938

V. Swamy Irrinki - Milpitas CA
Tuan L. Phan - San Jose CA
William D. Schwarz - San Jose CA

LSI Logic Corporation - Milpitas CA

G11C 700

365201

An efficient methodology for detecting and rejecting faulty integrated circuits with embedded memories utilizing stress factors during the manufacturing production testing process. In the disclosed embodiment of the invention, a stress factor is applied to an integrated circuit having built-in-self-test (BIST) circuitry and built-in-self-repair (BISR) circuitry. A BIST run is then performed on a predetermined portion of the integrated circuit to detect a set of faulty memory locations. The results of this first BIST run are stored. A second condition is applied to the die and a second BIST run is executed to generate a second set of faulty memory locations. The results of the second BIST run are stored and compared with the first result. If the results differ, the integrated circuit is rejected. Thus, a methodology for screening out field errors at the factory is disclosed using BIST/BISR circuitry.

6300769, Oct 9, 2001

Dec 17, 1999

9/466519

Tuan Phan - San Jose CA

LSI Logic Corporation - Milpitas CA

H01H 3102

324537

Accordingly, there is disclosed herein a fast word compare circuit suitable for use in a BIST or BISR environment. In one embodiment, the comparator includes a front end and a zero-detector circuit. The front end receives two or more words and compares them bitwise, generating a set of bit match signals that indicate which bits match. The zero detector receives the bit match signals from the front end and asserts an output signal when all the bit match signals indicate a match. The front end may consist of a set of exclusive-or (XOR) gates, each configured to generate a bit match signal from respective bits of the input words. The zero detector may include a set of bit transistors coupled in parallel between a first node and ground. Each bit transistor receives a respective bit match signal and conducts when the respective bit match signal is asserted. A first clock transistor may be coupled between the first node and a second node and configured to conduct when a clock signal is asserted, and a second clock transistor may be coupled between a positive source voltage and the second node and configured to conduct when the clock signal is de-asserted.