TRONG D NGUYEN
Electrician at Crse Dr, Houston, TX

5619158, Apr 8, 1997

Aug 18, 1995

8/516704

Humberto F. Casal - Austin TX
Joel R. Davidson - Austin TX
Hehching H. Li - Austin TX
Yuan C. Lo - Austin TX
Trong D. Nguyen - Webster TX
Campbell H. Snyder - Austin TX
Nandor G. Thoma - Plano TX

International Business Machines Corp. - Armonk NY

H03K 513

327292

A clocking system for complex electronic devices is created in an hierarchial manner whereby the master clock pulse is provided to a plurality of digital pulse aligners which in turn provide phase aligned clock signals at the field replaceable unit level to either a slave clock or a digital phase aligner. The slave clock or the digital phase aligner at the field replaceable unit level in turn provides an aligned clock pulse to a timing node on respective chips. A third level of the hierarchy provides similarly aligned pulses to individual using-circuits on the chips of the system. The digital phase aligner, aligning the output pulse at the timing node of the next level with the reference pulses being provided to the digital phase aligner at each level, insures that the timing pulses arriving at the utilizing circuits are synchronously aligned with clock pulses of the master clock. The system provides dramatic simplification of replacement of either field replaceable units or individual components within field replaceable units. The system is self-phasing and self-correcting to accommodate timing misalignments caused by any variations in the timing delays at all levels, thereby reducing the jitter that must be accommodated.

5524035, Jun 4, 1996

Aug 10, 1995

8/513245

Humberto F. Casal - Austin TX
Rafey Mahmud - Austin TX
Trong Nguyen - Houston TX
Mark L. Shulman - Staatsburg NY
Nandor G. Thoma - Plano TX

International Business Machines Corporation - Armonk NY

H03K 2100

377 47

A dynamically switchable clock system having a symmetrical output signal includes a frequency doubler which couples the input frequency to provide greater resolution and synchronization of an output signal to an input signal in the frequency divider and the facility to handle odd divides as even divides at double frequency, a counter controlled by a divisor select signal, first and second compare circuits which compare against the preprogrammed count for division, the compare circuits receiving an input from the divisor select circuits, and having outputs to a counter reset line and to an output clock S/R latch which provides the frequency divided symmetrical output signal.

5917356, Jun 29, 1999

Sep 11, 1995

8/526395

Humberto Felipe Casal - Austin TX
Hehching Harry Li - Austin TX
Trong Duc Nguyen - Webster TX

International Business Machines Corp. - Armonk NY

H03K 300

327236

A phase detector circuit receives both a reference clock signal and a sense clock signal and produces a synchronization signal if the sense and reference clock signals are in phase within a specified tolerance. A lead/lag signal is provided to a skew control circuit and accompanying delay circuits to increase or decrease the amount of delay on the reference clock signal and the sense clock signal if the two signals are not in phase within the specified tolerance. The sense clock signal is a feedback signal returned from logic circuitry, which originally receives the reference clock signal, which may be supplied by a master clock signal within a processor.

5822596, Oct 13, 1998

Nov 6, 1995

8/554206

Humberto Felipe Casal - Austin TX
Hehching Harry Li - Austin TX
Trong Duc Nguyen - Webster TX
Nandor Gyorgy Thoma - Plano TX

International Business Machines Corporation - Armonk NY

H03K 2100, G06F 1300

39575004

During power up and power down of logic circuitry implemented in CMOS, the clock signal supplied to the logic circuitry is incremented and decremented, respectively, to avoid a sudden application or removal of the clock signal to the logic circuitry.