TIMOTHY JAMES SOUTHGATE
Pilots at Woodside Rd, Redwood City, CA

6588004, Jul 1, 2003

Jul 7, 2000

09/611376

Timothy J. Southgate - Redwood City CA
Michael Wenzler - Piedmont CA

Altera Corporation - San Jose CA

G06F 1750

716 11, 716 7, 716 3, 716 18, 716 2

A method is described herein for designing a circuit using graphic editor software. A graphic design file is generated corresponding to a block diagram created in a graphical user interface associated with the graphic editor software. The block diagram includes a plurality of blocks and a plurality of conduits interconnecting the blocks. A block design file is generated in one of a plurality of formats for each of selected ones of the plurality of blocks in the block diagram. Each of the block design files corresponds to an implementation of its corresponding block. Modifications to any of the graphic design file and the block design files are incorporated into each other under software control.

6205579, Mar 20, 2001

Oct 27, 1997

8/958414

Timothy J. Southgate - Redwood City CA

Altera Corporation - San Jose CA

G06F 9445

717 11

A method for upgrading software is described. According to the invention, in response to operation of the software on a first platform, a connection is established between the first platform and a remote platform. Where first version data associated with the software are different from second version data from the remote platform, a portion of the software is overwritten with first updated code from the remote platform.

2008030, Dec 4, 2008

Aug 15, 2008

12/192880

Peter Mattson - Sunnyvale CA, US
Timothy J. Southgate - Woodside CA, US

G06F 12/02

711170, 711E12002

Within a data processing system, a user-entered data declaration within a program source file is inspected to determine whether a first qualifier is provided with or omitted from the user-entered data declaration. If the first qualifier is provided, an unreserved data storage location disposed within a data-processing integrated-circuit (IC) device is identified and allocated for storage of data associated with the user-entered data declaration.

6408432, Jun 18, 2002

Apr 19, 2000

09/552575

Alan L. Herrmann - Sunnyvale CA
Timothy J. Southgate - Redwood City CA

Altera Corporation - San Jose CA

G06F 945

717139, 717124, 714725, 326 39

An apparatus and method for in-system programming of programmable devices includes a device configuration program with adaptive programming source code instructions that characterize device configuration instructions and data. The adaptive source code instructions may include conditional branches, subroutines, variables, configurable arrays, integer operators, and Boolean operators. These features allow for more compact and efficient device configuration instructions and data. An interpreter converts the device configuration program into formatted device configuration instructions and data. The formatted device configuration instructions and data are preferably compatible with IEEE 1149. 1 JTAG-BST specifications. The formatted device configuration instructions and data are used to program a programmable device in the manner specified by the adaptive programming source code instructions.

RE42444, Jun 7, 2011

Jan 30, 2009

12/322325

Stephen J. Smith - Los Gatos CA, US
Timothy J. Southgate - Woodside CA, US

Altera Corporation - San Jose CA

G06F 9/00, G06F 3/00

713 1, 713100, 710 8

A reconfigurable computer system based on programmable logic is provided. A system design language may be used to write applications. The applications may be automatically partitioned into software components and programmable logic resource components. A virtual computer operating system may be provided to schedule and allocate system resources. The virtual computer operating system may include a virtual logic manager that may increase the capabilities of programmable logic resources in the system.

2010025, Oct 7, 2010

Aug 6, 2009

12/537195

Brucek Khailany - San Francisco CA, US
Nuwan Jayasena - Sunnyvale CA, US
Brian Pharris - Sunnyvale CA, US
Timothy Southgate - Woodside CA, US

G06F 12/02

711163, 711167, 711154, 711E12002

An application programming interface is disclosed for loading and storing multidimensional arrays of data between a data parallel processing unit and an external memory. Physical addresses reference the external memory and define two-dimensional arrays of data storage locations corresponding to data records. The data parallel processing unit has multiple processing lanes to parallel process data records residing in respective register files. The interface comprises an X-dimension function call parameter to define an X-dimension in the memory array corresponding to a record for one lane and a Y-dimension function call parameter to define a Y-dimension in the memory array corresponding to the record for one lane. The X-dimension and Y-dimension function call parameters cooperate to generate memory accesses corresponding to the records.

8438365, May 7, 2013

Oct 9, 2007

11/973895

Timothy J. Southgate - Woodside CA, US

Calos Fund Limited Liability Company - Dover DE

G06F 12/00

711217, 711E12001

A method of loading data into register files that correspond to respective execution units within a data-parallel processor. After receiving a first set of parameters that specify a subset of data within a first memory, the first set of parameters are compared to a plurality of sets of conditions that correspond to respective patterns of data. The first set of parameters is then converted to a second set of parameters in accordance with one of the sets of conditions satisfied by the first set of parameters. A sequence of memory addresses are generated based on the second set of parameters. Data is retrieved from locations within the first memory specified by the sequence of memory addresses and loaded into register files that correspond to respective execution units within a processor.

6120550, Sep 19, 2000

Oct 27, 1997

8/958432

Timothy J. Southgate - Redwood City CA
Michael Wenzler - Piedmont CA

Altera Corporation

G06F 1750

716 11

A method is described herein for generating a design file corresponding to a design entity in a logic design. An input and an output are specified for the design entity. A design file type is specified. The design file is created and a design file template corresponding to the design file type is copied into the design file. The design file template includes formatting corresponding to the design file type. The input and the output are instantiated in the design file. The designer may then completely specify the design entity in the design file.

6311309, Oct 30, 2001

Oct 27, 1997

8/958777

Timothy J. Southgate - Redwood City CA

Altera Corporation - San Jose CA

G06F 1750

716 1

A method for simulating a portion of a circuit design is described. The circuit design includes a plurality of design files each corresponding to one of a plurality of design entities in the circuit design. A subset of the design entities is selected. The subset of the design entities corresponds to the portion of the circuit design to be simulated. In response to selection of the subset of the design entities, a netlist is generated under software control directly from the design files associated with the subset of the design entities. The portion of the circuit design is then simulated using the netlist.

2008030, Dec 4, 2008

Aug 15, 2008

12/192894

Timothy J. Southgate - Woodside CA, US
Raghunath Rao - Austin TX, US
Kenneth Hesky - Sunnyvale CA, US

G06F 9/46

718105

A system for multiple task management between processors includes a first processing device for executing tasks. A respective storage element is provided for storing one or more commands from each of the tasks. A command dispatcher is provided for selectively transferring a command from one of the storage elements to a command queue provided within a second processing device.