TIMOTHY C JORDAN, CRNA
Nursing at Medical Pkwy, Austin, TX
License number
Texas 37629
Category
Nursing
Type
Nurse Anesthetist, Certified Registered
Address
Address
3705 Medical Pkwy SUITE 570, Austin, TX 78705
Phone
(512) 454-2454
(512) 454-1532 (Fax)
(512) 454-1532 (Fax)
Professional information
Timothy C Jordan, Austin TX - CRNA (Certified registered nurse anesthetist)
Specialties:
Nurse Anesthesiology
Address:
3705 Medical Pkwy STE 570, Austin 78705
(512) 454-2454 (Phone), (512) 454-1532 (Fax)
(512) 454-2454 (Phone), (512) 454-1532 (Fax)
Languages:
English
Linearized Digital Phase-Locked Loop
US Patent:
6366145, Apr 2, 2002
Filed:
Dec 21, 2000
Appl. No.:
09/745660
Inventors:
Bertrand J. Williams - Austin TX
Kamal Dalmia - Sunnyvale CA
Terry D. Little - Austin TX
Timothy D. Jordan - Austin TX
Kamal Dalmia - Sunnyvale CA
Terry D. Little - Austin TX
Timothy D. Jordan - Austin TX
Assignee:
Cypress Semiconductor Corp. - San Jose CA
International Classification:
H03L 706
US Classification:
327156, 327144, 331 17, 331 1 A, 377 78
Abstract:
An apparatus for synchronizing a clock signal to a data signal. The apparatus comprises a detector and a control circuit. The detector may be configured to produce a value representing a position of an edge of said data signal based upon a state of said clock signal. The control circuit may be configured to adjust the clock signal based upon the value.
Timothy C Jordan, Austin TX
Specialties:
Nurse Practitioner
Address:
3705 Medical Pkwy, Austin, TX 78705
Linearized Digital Phase-Locked Loop Method
US Patent:
6950484, Sep 27, 2005
Filed:
Dec 22, 2000
Appl. No.:
09/747188
Inventors:
Timothy D. Jordan - Austin TX, US
Terry D. Little - Austin TX, US
Kamal Dalmia - Sunnyvale CA, US
Terry D. Little - Austin TX, US
Kamal Dalmia - Sunnyvale CA, US
Assignee:
Cypress Semiconductor Corp. - San Jose CA
International Classification:
H04L007/00
US Classification:
375355, 327 24
Abstract:
A method for synchronizing a clock signal to a data signal, comprising the steps of (A) detecting an edge of the data signal, (B) determining whether a position of the edge is within a zone and (B) if the edge is not within the zone, adjusting the clock signal towards the position of the edge.
Linearized Digital Phase-Locked Loop
US Patent:
6993105, Jan 31, 2006
Filed:
Dec 22, 2000
Appl. No.:
09/747257
Inventors:
Terry D. Little - Austin TX, US
Bertrand J. Williams - Austin TX, US
Kamal Dalmia - Sunnyvale CA, US
Timothy D. Jordan - Austin TX, US
Bertrand J. Williams - Austin TX, US
Kamal Dalmia - Sunnyvale CA, US
Timothy D. Jordan - Austin TX, US
Assignee:
Cypress Semiconductor Corp. - San Jose CA
International Classification:
H04L 7/00
US Classification:
375360, 375371, 370516
Abstract:
A method of synchronizing a clock signal to a data signal, comprising the steps of (A) detecting a first edge of the data signal and a position of the first edge, (B) determining if the position is within a zone, (C) if the edge is not within the zone, adjusting the clock signal towards the position of the edge, (D) detecting a second edge of the data signal and a position of the second edge, (E) determining a in value indicating a position of the second edge, (F) adding the first value to a second value, wherein the second value indicates a position of a third edge of the data signal and (G) adjusting the clock signal based on the result of step (F).