DR. THOMAS WILLIAM HUFF, M.D.
Medical Practice at Sam Jackson Park Rd, Portland, OR

6502115, Dec 31, 2002

Apr 27, 2001

09/845610

Mohammad A. F. Abdallah - Folsom CA
Hsien-Cheng E. Hsieh - Gold River CA
Thomas R. Huff - Portland OR
Vladimir Pentkovski - Folsom CA
Patrice Roussel - Portland OR
Shreekant S. Thakkar - Portland OR

Intel Corporation - Santa Clara CA

G06F 700

708204, 712220

A method and instruction for converting a number between a floating point format and an integer format are described. Numbers are stored in the integer format in a register of a first set of architectural registers in a packed format. At least one of the numbers in the integer format is converted to at least one number in the floating point format. The numbers in the floating point format are placed in a register of a second set of architectural registers in a packed format.

6798364, Sep 28, 2004

Feb 5, 2002

10/068050

Yen-Kuang Chen - Sunnyvale CA
Matthew J. Holliman - Sunnyvale CA
Herbert Hum - Portland OR
Per H. Hammarlund - Hillsboro OR
Thomas Huff - Portland OR
William W. Macy - Palo Alto CA

Intel Corporation - Santa Clara CA

H03M 740

341 67, 37524023

A method and apparatus for variable length coding is described. A method comprises receiving a group of data having a group of set values, identifying a group of positions of the group of set values within the group of data without branching, for each of the group of positions, encoding a run of non-set values preceding each of the group of positions.

6185670, Feb 6, 2001

Oct 12, 1998

9/170136

Thomas R. Huff - Portland OR
Shreekant S. Thakkar - Portland OR
Roger A. Golliver - Beaverton OR

Intel Corporation - Santa Clara CA

G06F 1500

712208

A method and apparatus for reducing the number of opcodes required in a computer architecture using an operation class code and an operation selector code. A processor contains a fetch unit which fetches instructions to be executed by the processor. An instruction may conform to an instruction format which includes a number of fields that specify an operation class code, an operation selector code, and one or more operands. The processor also contains a decoder which uses the operation class code to generate a single execution flow that is capable of executing a class of similar operations. The single execution flow, in the form of execution control information, is sent to an execution unit along with the associated operands. The operation selector code is also passed to the execution unit. The execution unit performs the specific operation identified by the operation selector code and execution control information.

6211892, Apr 3, 2001

Mar 31, 1998

9/053389

Thomas Huff - Portland OR
Shreekant S. Thakkar - Portland OR

Intel Corporation - Santa Clara CA

G06T 1522

345524

An apparatus and method for performing an intra-add operation on packed data using computer-implemented steps is described. A processor is coupled to a hardware unit which transmits data representing graphics to another computer or display. A storage device coupled to the processor, has stored therein a routine, which, when executed by the processor, causes the processor to generate the data. The routine causes the processor to at least access a first packed data operand having at least one pair of data elements; swap positions of the data elements within the at least one pair of data elements to generate a second packed data operand, add data elements starting at the same bit positions from the first and second packed data operands to generate a third packed data operand.

6275904, Aug 14, 2001

Mar 31, 1998

9/053385

Srinivas Chennupaty - Portland OR
Shreekant S. Thakkar - Portland OR
Thomas Huff - Portland OR
Vladimir Pentkovski - Folsom CA

Intel Corporation - Santa Clara CA

G06F 1208

711138

A computer system and method for providing cache memory management. The computer system comprises a main memory having a plurality of main memory addresses each having a corresponding data entry, and a processor coupled to the main memory. At least one cache memory is coupled to the processor. The at least one cache memory has a cache directory with a plurality of addresses and a cache controller having a plurality of data entries corresponding to the plurality of addresses. The processor receives an instruction having an operand address and determines if the operand address matches one of the plurality of addresses in the cache directory. If so, the processor updates a data entry in the cache controller corresponding to the matched address. Otherwise, a data entry corresponding to the operand address in the main memory is updated.

6292815, Sep 18, 2001

Apr 30, 1998

9/069796

Mohammad A. F. Abdallah - Folsom CA
Hsien-Cheng E. Hsieh - Gold River CA
Thomas R. Huff - Portland OR
Vladimir Pentkovski - Folsom CA
Patrice Roussel - Portland OR
Shreekant S. Thakkar - Portland OR

Intel Corporation - Santa Clara CA

G06F 9302

708204

A method and instruction for converting a number between a floating point format and an integer format are described. Numbers are stored in the integer format in a register of a first set of architectural registers in a scalar format. At least one of the numbers in the scalar format is converted to a number in the floating point format. The number in the floating point format is placed in a register of a second set of architectural registers in a packed format.

6898700, May 24, 2005

Mar 31, 1998

09/053398

Shreekant S. Thakkar - Portland OR, US
Patrice L. Roussel - Portland OR, US
Thomas Huff - Portland OR, US
Bryant E. Bigbee - Aloha OR, US
Stephen A. Fischer - Shingle Springs CA, US

Intel Corporation - Santa Clara CA

G06F009/22

712244

The present invention discloses a method and apparatus for saving and restoring registers. A single instruction is decoded. The single instruction moves contents of a plurality of registers associated with a functional unit in a processor to a memory; the processor operates under a plurality of operational modes and operand sizes. The single instruction arranges the contents in the memory according to a predetermined format into a plurality of groups, each group is aligned at an address boundary which corresponds to a multiple of 2bytes. The predetermined format is constant for the plurality of operational modes and operand sizes. The single instruction retains the contents of the plurality of registers after moving.