DR. THOMAS HOWARD JONES, M.D.
Psychiatric at Eastowne Dr, Chapel Hill, NC

License number
North Carolina 35933
Category
Psychiatric
Type
Psychiatry
Address
Address
727 Eastowne Dr SUITE 300A, Chapel Hill, NC 27514
Phone
(919) 489-5455
(919) 489-5457 (Fax)

Personal information

See more information about THOMAS HOWARD JONES at radaris.com
Name
Address
Phone
Thomas Jones
509 Webber St, Shelby, NC 28152
(704) 267-9523
Thomas Jones, age 50
5037 Dawn Piper Dr, Raleigh, NC 27613
Thomas Jones
503 Beckner St, Lexington, NC 27292
(336) 248-6839
Thomas Jones, age 72
503 Watkins Rd, Hillsborough, NC 27278
Thomas Jones
503 Fairley St, Laurinburg, NC 28352
(910) 987-1424

Professional information

Thomas Howard Jones Photo 1

Thomas Howard Jones, Chapel Hill NC

Specialties:
Internist
Address:
727 Eastowne Dr, Chapel Hill, NC 27514


Thomas Jones Photo 2

Digital Data Processing System Utilizing A Unique Arithmetic Logic Unit For Handling Uniquely Identifiable Addresses For Operands And Instructions

US Patent:
4445177, Apr 24, 1984
Filed:
May 22, 1981
Appl. No.:
6/266411
Inventors:
Richard G. Bratt - Wayland MA
Stephen I. Schleimer - Chapel Hill NC
John F. Pilat - Raleigh NC
Richard A. Belgard - Saratoga CA
Steven J. Wallach - Saratoga CA
Gerald F. Clancy - Saratoga CA
Craig J. Mundie - Cary NC
David H. Bernstein - Ashland MA
Edward S. Gavrin - Lincoln MA
Thomas M. Jones - Chapel Hill NC
Brett L. Bachman - Boston MA
Assignee:
Data General Corporation - Westboro MA
International Classification:
G06F 922
US Classification:
364200
Abstract:
A data processing system having a flexible internal structure, protected from and effectively invisible to users, with multilevel control and stack mechanisms and capability of performing multiple, concurrent operations, and providing a flexible, simplified interface to users. The system is internally comprised of a plurality of separate, independent processors, each having a separate microinstruction control and at least one separate, independent port to a central communications and memory node. The communications and memory node is an independent processor having separate, independent microinstruction control and comprised of a plurality of independently operating, microinstruction controlled processors capable of performing multiple, concurrent memory and communications operations. Addressing mechanisms allow permanent, unique indentification of information as objects and an extremely large address space accessible and common to all such systems. Addresses are independent of system physical configuration and, as particularly described withreference to the invention herein, indentify locations of object information to be accessed by utilizing address formats which comprise an object field, offset field and a length field so that information can be identified to bit granular level and to information type and format.


Thomas Jones Photo 3

Digital Data Processing System Respoonsive To Instructions Containing Operation Code Modifiers

US Patent:
4466057, Aug 14, 1984
Filed:
Sep 15, 1981
Appl. No.:
6/303312
Inventors:
David L. Houseman - Westchester PA
Thomas M. Jones - Chapel Hill NC
Michael S. Richmond - Beaverton OR
John F. Pilat - Raleigh NC
Assignee:
Data General Corporation - Westboro MA
International Classification:
G06F 700
US Classification:
364200
Abstract:
A system for modifying the manner in which a processor in a digital computer system responds to operation codes in certain instructions. All instructions to which the system responds have operation code syllables containing an operation code and an operation code modifier. In instructions having certain operation codes, the operation code modifier contains a value which modifies the manner in which the processor responds to the operation code. When the processor receives an instruction having such an operation code, a part of the processor which is responsive to the operation code modifier employs the value in the operation code modifier to modify the interpretation of the instruction by the processor. The manner in which the value is employed depends on the operation code. Several uses of the operation code modifier are disclosed.


Thomas Jones Photo 4

Digital Data Processing System

US Patent:
4493024, Jan 8, 1985
Filed:
May 22, 1981
Appl. No.:
6/266406
Inventors:
Ward Baxter - Carlisle MA
Gerald F. Clancy - Saratoga CA
Ronald H. Gruner - Cary NC
Craig J. Mundie - Cary NC
Brett L. Bachman - Boston MA
Stephen R. Redfield - San Jose CA
William N. Coder - Raleigh NC
Thomas M. Jones - Chapel Hill NC
David L. Houseman - Cary NC
Charles J. Young - Berlin MA
Steven M. Haeffele - Cary NC
Assignee:
Data General Corporation - Westboro MA
International Classification:
G06F 1300
US Classification:
364200
Abstract:
A data processing system having a flexible internal structure, protected from and effecitvely invisible to users, with multilevel control and stack mechanisms and capability of performing multiple, concurrent operations, and providing a flexible, simplified interface to users. The system is internally comprised of a plurality of separate, independent processors, each having a separate microinstruction control and at least one separate, independent port to a central communications and memory node. The communications and memory node is an independent processor having separate, independent microinstruction control and comprised of a plurality of independently operating, microinstruction controlled processors capable of performing multiple, concurrent memory and communications operations. Addressing mechanisms allow permanent, unique identification of information and an extremely large address space accessible and common to all such systems. Addresses are independent of system physical configuration.


Thomas Jones Photo 5

Digital Data Processing System With Tripartite Description-Based Addressing Multi-Level Microcode Control, And Multi-Level Stacks

US Patent:
4532586, Jul 30, 1985
Filed:
May 22, 1981
Appl. No.:
6/266401
Inventors:
Richard G. Bratt - Wayland MA
Stephen I. Schleimer - Chapel Hill NC
Edward S. Gavrin - Lincoln MA
John F. Pilat - Raleigh NC
Steven J. Wallach - Saratoga CA
Lawrence H. Katz - Oregon City OR
Douglas M. Wells - Chapel Hill NC
Gerald F. Clancy - Saratoga CA
Craig J. Mundie - Cary NC
David H. Bernstein - Ashland MA
Thomas M. Jones - Chapel Hill NC
Brett L. Bachman - Boston MA
Assignee:
Data General Corporation - Westboro MA
International Classification:
G06F 922
US Classification:
364200
Abstract:
A digital computer system in which data storage is referred to by a descriptor comprising an object number denoting a variable-length block of storage, an offset indicating how far into that block a desired data item begins, and a length field denoting the length of the desired data item. Separate means exist for manipulating each of the three descriptor portions, thus facilitating repetitive operations on related or contiguous operands. Various levels of microcode control are included. Each level of microcode control has its own stack, facilitating interrupts between levels. Stacks are duplicated in "secure stacks" in memory to protect against loss of state data from the stacks.


Thomas Jones Photo 6

Digital Data Processing System Capable Of Executing A Plurality Of Internal Language Dialects

US Patent:
4618925, Oct 21, 1986
Filed:
Jul 13, 1984
Appl. No.:
6/630991
Inventors:
Richard G. Bratt - Wayland NC
Ronald H. Gruner - Cary NC
Thomas M. Jones - Chapel Hill NC
James T. Nealon - Cary NC
Assignee:
Data General Corporation - Westboro MA
International Classification:
G06F 916
US Classification:
364200
Abstract:
The processor of the present invention can execute any of a plurality of dialects of "S-Language" instructions. S-Languages are of a higher order than typical machine languages but of a lower order than the user's own high order language. They can be tailored for compatibility with user high order languages. Each instruction of a particular S-Language is interpreted by a sequence of microinstructions. In the processor of the present invention, dispatching to the microinstruction sequencer is controlled jointly by the instruction bit pattern and the current contents of a dialect register. Each procedure to be executed carries with it information from which the appropriate contents of the dialect register may be determined. Thus, the processor of the present invention can always operate as an effective optimum processor for executing the procedure regardless of the source language chosen for writing that procedure.


Thomas Jones Photo 7

Digital Data Processing System Having Unique Addressing Means And Means For Identifying And Accessing Operands

US Patent:
4493023, Jan 8, 1985
Filed:
May 22, 1981
Appl. No.:
6/266403
Inventors:
Edward S. Gavrin - Lincoln MA
Richard G. Bratt - Wayland MA
Stephen I. Schleimer - Chapel Hill NC
John F. Pilat - Raleigh NC
Michael S. Richmond - Pittsboro NC
Walter A. Wallach - Raleigh NC
Richard A. Belgard - Saratoga CA
David A. Farber - Durham NC
John K. Ahlstrom - Mountain View CA
Steven J. Wallach - Saratoga CA
Gerald F. Clancy - Saratoga CA
Craig J. Mundie - Cary NC
Thomas M. Jones - Chapel Hill NC
Brett L. Bachman - Boston MA
David H. Bernstein - Ashland MA
Assignee:
Data General Corporation - Westboro MA
International Classification:
G06F 930
US Classification:
364200
Abstract:
A data processing system having a flexible internal structure, protected from and effectively invisible to users, with multilevel control and stack mechanisms and capability of performing multiple, concurrent operations, and providing a flexible, simplified interface to users. The system is internally comprised of a plurality of separate, independent processors, each having a separate microinstruction control and at least one separate, independent port to a central communications and memory node. The communications and memory node is an independent processor having separate, independent microinstruction control and comprised of a plurality of independently operating, microinstruction controlled processors capable of performing multiple, concurrent memory and communications operations. Addressing mechanisms allow permanent, unique identification of information and an extremely large address space accessible and common to all such systems. Addresses are independent of system physical configuration.


Thomas Jones Photo 8

Data Processing System Having Unique Microinstruction Control And Stack Means

US Patent:
4939640, Jul 3, 1990
Filed:
Apr 5, 1984
Appl. No.:
6/597195
Inventors:
Brett L. Bachman - Boston MA
Richard A. Belgard - Saratoga CA
Richard G. Bratt - Wayland MA
Thomas M. Jones - Chapel Hill NC
Assignee:
Data General Corporation - Westboro MA
International Classification:
G06F 0922, G06F 0946
US Classification:
364200
Abstract:
A data processing system which includes a memory and a processor comprising at least two execution units. The system further includes a microcode control unit for storing sequences of microinstructions and an execution microinstruction stack containing at least one stack frame containing the machine state of a first execution unit when the execution of a microinstruction has been interrupted. A memory microinstruction stack is provided to store a plurality of stack frames, stack frames being transferrable between the execution microinstruction stack and the memory microinstructiion stack. The microcode control unit contains sequences of monitor microinstructions and has associated with it a minotor microinstruction stack for storing the machine state of the first execution unit when the execution of a monitor microinstruction has been interrupted. A second execution unit for executing primarily arithmetic microinstructions includes an execution storage unit containing the current machine state of the second execution unit and an arithmetic stack which stores the machine state of the second execution unit when it has executed a previous arithmetic microinstruction. The memory includes a memory arithmetic stack containing further arithmetic stack frames, stack frames being transferrable between the execution storage unit and the memory arithmetic stack.


Thomas Jones Photo 9

Digital Data Processing System Using Unique Alu Register Files And Micro-Instruction Stacks

US Patent:
4480306, Oct 30, 1984
Filed:
May 22, 1981
Appl. No.:
6/266425
Inventors:
Brett L. Bachman - Boston MA
Richard A. Belgard - Saratoga CA
David H. Bernstein - Ashland MA
Richard G. Bratt - Wayland MA
Gerald F. Clancy - Saratoga CA
Edward S. Gavrin - Lincoln MA
Thomas M. Jones - Chapel Hill NC
Lawrence H. Katz - Oregon City OR
Craig J. Mundie - Cary NC
John F. Pilat - Raleigh NC
Stephen I. Schleimer - Chapel Hill NC
Steven J. Wallach - Saratoga CA
Walter A. Wallach - Raleigh NC
Douglas M. Wells - Chapel Hill NC
Assignee:
Data General Corporation - Westboro MA
International Classification:
G06F 922
US Classification:
364200
Abstract:
A data processing system having a flexible internal structure, protected from and effectively invisible to users, with multilevel control and stack mechanisms and capability of performing multiple, concurrent operations, and providing a flexible, simplified interface to users. The system is internally comprised of a plurality of separate, independent processors, each having a separate microinstruction control and at least one separate, independent port to a central communications and memory node. The communications and memory node is an independent processor having separate, independent microinstruction control and comprised of a plurality of independently operating, microinstruction controlled processors capable of performing multiple, concurrent memory and communications operations. Addressing mechanisms allow permanent, unique identification of information as objects and an extremely large address space accessible and common to all such systems. Addresses are independent of system physical configuration and, as particularly described with reference to the invention herein, identify locations of object information to be accessed by utlizing address formats which comprise an object field, offset field and a length field so that information can be identified to bit granular level and to information type and format.


Thomas Jones Photo 10

Speedometer Scale Conversion Kit And Method

US Patent:
4092191, May 30, 1978
Filed:
Sep 28, 1977
Appl. No.:
5/837463
Inventors:
Thomas L. Jones - Chapel Hill NC
International Classification:
G01P 108
US Classification:
156 64
Abstract:
A speedometer scale conversion kit and method of utilization of the components of such kit comprises the present invention. The conversion kit is composed of a step-by-step instructional sheet, a decal card and a cardboard strip having printed guide indicia. The instruction sheet provides the step-by-step method for forming the cardboard strip into a ten kilometer gauge, using the gauge to measure off and mark ten kilometer spacings on the transparent face cover of the speedometer, and for then removing and placing the appropriate kilometer number decal on the premarked face of the speedometer.