THOMAS H JONES, DDS
Dentist at Scottsdale Rd, Scottsdale, AZ
License number
Arizona 3472
Category
Dentist
Type
General Practice
Address
Address
3501 N Scottsdale Rd STE 242, Scottsdale, AZ 85251
Phone
(480) 946-8883
(480) 946-8887 (Fax)
(480) 946-8887 (Fax)
Organization information
See more information about THOMAS H JONES at bizstanding.comThomas H Jones DDS
3501 N Scottsdale Rd, Scottsdale, AZ 85251
Industry:
Dentist's Office
Phone:
(480) 946-8883 (Phone)
Owner, Family And General Dentistry:
Thomas H. Jones (Owner, Family And General Dentistry)
Professional information
Dr. Thomas H Jones, Scottsdale AZ - DDS (Doctor of Dental Surgery)
Specialties:
Dentistry
Address:
3501 N Scottsdale Rd STE 242, Scottsdale 85251
(480) 946-8883 (Phone), (480) 946-8887 (Fax)
(480) 946-8883 (Phone), (480) 946-8887 (Fax)
Languages:
English
Thomas Martin Jones, Scottsdale AZ - Lawyer
Address:
Automon Corporation
10450 N 74Th St STE 210, Scottsdale 85258
(480) 368-8555
10450 N 74Th St STE 210, Scottsdale 85258
(480) 368-8555
Licenses:
New York - Currently registered 1987
Education:
Washington Lee
Thomas Howard Jones, Scottsdale AZ
Specialties:
Dentist
Address:
3501 N Scottsdale Rd, Scottsdale, AZ 85251
Method For Determining Timing Delays Associated With Placement And Routing Of An Integrated Circuit
US Patent:
5629860, May 13, 1997
Filed:
May 16, 1994
Appl. No.:
8/242984
Inventors:
Thomas R. Jones - Scottsdale AZ
Steven L. Crain - Chandler AZ
Joseph J. Burkis - Hilton NY
Steven L. Crain - Chandler AZ
Joseph J. Burkis - Hilton NY
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
G11C 702
US Classification:
364490
Abstract:
The present invention provides a method for determining timing delays associated with the placement and routing delays of an integrated circuit. In particular, the present invention determines the area of each region wherein a region includes a group or subgroup of circuit elements for use in designing an integrated circuit. Once the area for each region is obtained, substantially more accurate and more design specific wireload model and net parasitics can be obtained. The wireload models or net parasitics can then be supplied to other CAE tools to create a modified netlist. Moreover, the present invention provides a process which allows the user to account for the RC time constant effects of wire delay on a hierarchical block basis thereby improving the accuracy of the wire placement and routing delay estimate while preserving the performance benefits of a traditional simplified equation.