Thomas Franklin Green
Engineers at Executive Ctr Dr, Austin, TX

5870578, Feb 9, 1999

Dec 9, 1997

8/987451

Rupaka Mahalingaiah - Austin TX
Thomas S. Green - Austin TX

Advanced Micro Devices, Inc. - Sunnyvale CA

G06F 930

395391

A microprocessor employs a set of symmetrical functional units, each of which is coupled into an issue position. Instructions are fetched and aligned to the issue positions. During clock cycles in which fewer than the maximum number of instructions are concurrently selected for dispatch to the issue positions, the microprocessor distributes the selected instructions among the issue positions in order to substantially equalize the number of instructions conveyed to each issue position over a number of clock cycles. For example, the microprocessor may employ a counter, each value of which indicates a different set of issue positions to which instruction(s) are to be distributed. The counter is incremented each time the value is used to select a distribution. The resources in each issue position may be used more efficiently due to the more even distribution of instructions among the issue positions.

6041405, Mar 21, 2000

Dec 18, 1997

8/993476

Thomas S. Green - Austin TX

Advanced Micro Devices, Inc. - Sunnyvale CA

G06F 938

712213

A microprocessor configured to predict the length of variable length instructions for decoding purposes by detecting patterns of instruction lengths that have been previously decoded. The microprocessor has a cache, an instruction length calculation unit, and a pattern detector. The instruction length calculation unit receives instruction bytes from the cache and generates an instruction length corresponding thereto. The pattern detector stores a plurality of instruction length sequences, each comprising an initial sequence and a final sequence. The pattern detector is configured to receive instruction lengths from the length calculation unit and compare them with the stored initial sequences. If the pattern detector finds a match, it outputs the corresponding final sequence for use as predicted instruction lengths. A method for using instruction length pattern detection for decoding is also disclosed.

5951671, Sep 14, 1999

Dec 18, 1997

8/993475

Thomas S. Green - Austin TX

Advanced Micro Devices, Inc. - Sunnyvale CA

G06F 1500

712 23

A multiprocessor system capable of sharing instruction predecode information is disclosed. By storing predecode information as it is calculated, and then allowing other processors in the system to access the information, subsequent prefetches of instructions are made without repeating predecode calculations. The multiprocessor system may comprise a bus connecting at least two microprocessors together. The microprocessors may be configured to generate predecode information for a plurality of instructions and then share the predecode information with other microprocessors coupled to the bus. The predecode information may be stored in a single storage location or in multiple locations, and the information may be stored internally within the microprocessors or externally. The microprocessors in the system may be configured to search for predecode information corresponding to instructions being accessed. The predecode information may comprise start and end bits, functional bits, valid masks, or other data related to alignment and decode of instructions.

6125441, Sep 26, 2000

Dec 18, 1997

8/992803

Thomas S. Green - Austin TX

Advanced Micro Devices, Inc. - Sunnyvale CA

G06F 938

712210

An instruction cache having a pattern detector for use in predicting the length of variable length instructions in a microprocessor. The instruction cache comprises an instruction length calculation unit and the pattern detector. The pattern detector is configured with a content addressable memory and update logic. The content addressable memory stores fetch addresses and instruction lengths calculated by the calculation unit. The content addressable memory compares particular fetch addresses that it receives with fetch addresses already stored and outputs corresponding predicted instruction length sequences. The content addressable memory may receive, compare, and store instruction lengths or instruction bytes in addition to, or in lieu of, fetch addresses. A neural network or other type of memory configuration may be used in place of the content addressable memory.

6253287, Jun 26, 2001

Sep 9, 1998

9/150310

Thomas S. Green - Austin TX

Advanced Micro Devices, Inc. - Sunnyvale CA

G06F 1204

711125

A microprocessor capable of predecoding variable-length instructions and storing them in a three-dimensional instruction cache is disclosed. The microprocessor may comprise a predecode unit, an instruction cache, and an address translation table. The predecode unit receives variable-length instructions from a main memory subsystem. These instructions are then predecoded by detecting instruction field boundaries within each variable-length instruction. Instructions fields that are not present in a particular instruction may be added by inserting padding constants so that the instruction matches a predetermined format having all instruction fields. The predecoded instruction is stored in the instruction cache, which may be logically and physically structured as a three-dimensional array. Each instruction is stored in the cache so that it has a fixed length in two dimensions. The address translation table maintains address translations for each instruction stored in the instruction cache.