THOMAS EDWARD SUTTON, M.D.
Marriage and Family Therapists at Southern Ave, Mesa, AZ

License number
Arizona 19546
Category
Osteopathic Medicine
Type
Family Medicine
Address
Address
2530 E Southern Ave, Mesa, AZ 85204
Phone
(480) 892-2323

Personal information

See more information about THOMAS EDWARD SUTTON at radaris.com
Name
Address
Phone
Thomas Sutton, age 61
4713 W Lavey Rd, Glendale, AZ 85306
(623) 703-9427
Thomas Sutton
3400 S Ironwood Dr LOT 2, Apache Jct, AZ 85120
(480) 593-5541
Thomas M Sutton, age 87
2248 Geneva Dr, Tempe, AZ 85282
(480) 838-2181
Thomas M Sutton, age 87
2105 25Th Pl, Phoenix, AZ 85008
(602) 685-1725
Thomas M Sutton
2105 25Th St, Phoenix, AZ 85008
(602) 685-1725

Professional information

Thomas E Sutton Photo 1

Dr. Thomas E Sutton, Mesa AZ - MD (Doctor of Medicine)

Specialties:
Family Medicine
Address:
Associates In Family Medicine
2530 E Southern Ave, Mesa 85204
(480) 892-2323 (Phone)
Certifications:
Family Practice, 2007
Awards:
Healthgrades Honor Roll
Languages:
English
Hospitals:
Associates In Family Medicine
2530 E Southern Ave, Mesa 85204
Banner Desert Medical Center
1400 South Dobson Rd, Mesa 85202
Education:
Medical School
University of Washington
Graduated: 1989
Phoenix Bapt Hosp


Thomas Edward Sutton Photo 2

Thomas Edward Sutton, Mesa AZ

Specialties:
Family Medicine
Work:
Associates In Family Medicine
2530 E Southern Ave, Mesa, AZ 85204
Education:
University of Washington (1989)


Thomas Sutton Photo 3

High Pressure Compatible Vacuum Chuck For Semiconductor Wafer Including Lift Mechanism

US Patent:
6722642, Apr 20, 2004
Filed:
Nov 6, 2002
Appl. No.:
10/289830
Inventors:
Thomas R. Sutton - Mesa AZ
Maximilan A. Biberger - Scottsdale AZ
Assignee:
Tokyo Electron Limited - Tokyo
International Classification:
B25B 1100
US Classification:
269 21, 269 47
Abstract:
A vacuum chuck for holding a semiconductor wafer during high pressure processing comprises a wafer platen, first through third lift pins, and an actuator mechanism. The wafer platen comprises a smooth surface, first through third lift pin holes, and a vacuum opening. In use, the vacuum opening applies vacuum to a surface of a semiconductor wafer, which chucks the semiconductor wafer to the wafer platen. The first through third lift pins mount within the first through third lift pin holes, respectively. The actuator mechanism couples the first through third lifting pins to the wafer platen. The actuator mechanism operates to extend the first through third lift pins in unison above the smooth surface of the wafer platen. The actuator mechanism operates to retract the first through third lift pins in unison to at least flush with the smooth surface of the wafer platen.


Thomas Sutton Photo 4

High Pressure Processing Chamber For Semiconductor Substrate Including Flow Enhancing Features

US Patent:
2002018, Dec 19, 2002
Filed:
Apr 10, 2002
Appl. No.:
10/121791
Inventors:
Maximilian Biberger - Scottsdale AZ, US
Frederick Layman - Fremont CA, US
Thomas Sutton - Mesa AZ, US
International Classification:
C23F001/00, C23C016/00
US Classification:
118/715000, 156/345330
Abstract:
A high pressure chamber for processing of a semiconductor substrate comprises a high pressure processing cavity, a plurality of injection nozzles, and first and second outlet ports. The high pressure processing cavity holds the semiconductor substrate during high pressure processing. The plurality of injection nozzles are oriented into the high pressure processing cavity at a vortex angle and are operable to produce a vortex over a surface of the semiconductor substrate. The first and second outlet ports are located proximate to a center of the plurality of injection nozzles and are operable in a first time segment to provide an operating outlet out of the first outlet port and operable in a second time segment to provide the operating outlet out of the second outlet port. In an alternative embodiment, an upper surface of the high pressure processing cavity comprises a height variation. The height variation produces more uniform molecular speeds for a process fluid flowing over the semiconductor substrate.


Thomas Sutton Photo 5

Gate Valve For Plus-Atmospheric Pressure Semiconductor Process Vessels

US Patent:
7494107, Feb 24, 2009
Filed:
Mar 30, 2005
Appl. No.:
11/094936
Inventors:
Alexei Sheydayi - Gilbert AZ, US
Thomas Sutton - Mesa AZ, US
Assignee:
Supercritical Systems, Inc. - Gilbert AZ
International Classification:
F16K 31/122
US Classification:
251 635, 251175, 251195, 414935
Abstract:
An isolation valve is preferably applied to the semiconductor industry for sealing a process vessel and also operates effectively at plus-atmospheric pressures. A double containment gate valve assembly includes a housing and a movable head assembly within the housing. The housing includes a first access opening and a second access opening. The head assembly is configurable into a first position where an access path through the first and second access openings is clear, and a second position where the access path is blocked.