THOMAS EDWARD ROTH
Pilots at 45 Ave, Portland, OR

5805859, Sep 8, 1998

Jun 7, 1995

8/477149

David J. Giramma - Portland OR
Thomas E. Roth - Portland OR
Oliver W. Kozber - Beaverton OR
Michael G. Robinson - Portland OR
David K. Johnson - Aloha OR

Synopsys, Inc. - Mountain View CA

G06F 9455, G06F 1750

395500

Described is a circuit modifier, network, and method for use with an event-driven digital logic simulator for enforcing consistent evaluation of input pin changes at state elements. The invention automatically interposes a fictitious 0-delay defer agent or processor, at the input pin to state elements such as D Flip-Flops. The interposition of the defer agent is handled by the simulator as follows. Defer agents schedule events related to input state changes on a special time or task queue which is not processed until after all other events have been executed for the current time, including any extra iterations caused by 0-delay scheduling activity. Defer agents or processors are placed in a simulation network just prior to one or more of the input pins of state elements, the effect of which is to delay events that normally would propagate to the input pin of a state element until all other normal simulation events are processed. Once the normal simulation events have been executed, the defer events are executed which permits the inputs of the state elements to change after other simulation events have been executed, thereby ensuring consistent evaluation of pin changes at state elements.

5726918, Mar 10, 1998

Jun 5, 1995

8/463881

David J. Giramma - Portland OR
Thomas E. Roth - Portland OR
Oliver W. Kozber - Beaverton OR

Synopsys, Inc. - Mountain View CA

G06F 1750

364578

Described is an invention that provides an efficient selection of timing statements for a logic cell in response to cell pin activity when such cell is implemented as one or more instances of simulator primitives. It does so by defining a first storage structure coupled with a logic processor coupled, in turn to a second storage structure. First storage structure defines plural bitfield arrays corresponding with a cell pin and a possible logic level or state, each bitfield array having an entry for an old or a former state of the pin, a next or new state of that pin and a stable state of that pin and each bitfield array defining an index to one or more memory-based look-up tables defining the number of a timing and/or constraint parameter for the given pin of the logic cell. Such timing parameters describe a delay between two pins of the cell, while such constraint parameters describe timing constraints for the logic cell such as setup times, hold times and minimum pulse width times. In accordance with a preferred embodiment of the invention, a set of rules is enforced by the logic processor during a digital logic simulation run to ensure that appropriate timing and constraint for the logic cell is maintained.