Thomas E. MacDonald
Engineers at 77 St, Minneapolis, MN
License number
South Dakota 12607
Expiration Date
Jul 31, 2017
Category
Professional Engineer
Type
Civil
Address
Address
4700 W 77Th St, Minneapolis, MN 55435
Phone
(952) 832-2729
Personal information
See more information about Thomas E. MacDonald at radaris.comName
Address
Phone
4825 Fremont Ave S, Minneapolis, MN 55419
4649 Decatur Ave N, Minneapolis, MN 55428
5324 Oliver Ave S, Minneapolis, MN 55419
Professional information
See more information about Thomas E. MacDonald at trustoria.com
System And Method Of Addressing Distributed Memory Within A Massively Parallel Processing System
System And Method Of Addressing Distributed Memory Within A Massively Parallel Processing System
US Patent:
5765181, Jun 9, 1998
Filed:
Dec 10, 1993
Appl. No.:
8/165118
Inventors:
Steven M. Oberlin - Chippewa Falls WI
Janet M. Eberhart - Saint Paul MN
Gary W. Elsesser - Richfield MN
Eric C. Fromm - Eau Claire WI
Thomas A. MacDonald - Minneapolis MN
Douglas M. Pase - Burnsville MN
Randal S. Passint - Chippewa Falls WI
Janet M. Eberhart - Saint Paul MN
Gary W. Elsesser - Richfield MN
Eric C. Fromm - Eau Claire WI
Thomas A. MacDonald - Minneapolis MN
Douglas M. Pase - Burnsville MN
Randal S. Passint - Chippewa Falls WI
Assignee:
Cray Research, Inc. - Eagan MN
International Classification:
G06F 1200
US Classification:
711 5
Abstract:
A system and address method for extracting a PE number and offset from an array index. According to one aspect of the present invention, a processing element number is assigned to each processing element, a local memory address is assigned to each memory location and a linearized index is assigned to each array element in an array. The processing element number of the processing element in which a particular array element is stored is computed as a function of a linearized index associated with the array element and a distribution specification associated with the array. In addition, a local memory address associated with the array element is computed as a function of the linearized index and the distribution specification.
Method For The Dynamic Allocation Of Array Sizes In A Multiprocessor System
Method For The Dynamic Allocation Of Array Sizes In A Multiprocessor System
US Patent:
5586325, Dec 17, 1996
Filed:
Dec 10, 1993
Appl. No.:
8/165379
Inventors:
Thomas A. MacDonald - Minneapolis MN
Janet M. Eberhart - Saint Paul MN
Douglas M. Pase - Burnsville MN
Janet M. Eberhart - Saint Paul MN
Douglas M. Pase - Burnsville MN
Assignee:
Cray Research, Inc. - Eagan MN
International Classification:
G06F 900
US Classification:
395706
Abstract:
A method of setting array boundaries in order to simplify addressing across processor elements in a distributed memory system having global addressing. Each dimension of an array is examined to determine a lower bound, a declared upper bound and an implicit upper bound. The lower bound and the declared upper bound in each dimension are used to set limits for operations on array elements while the implicit upper bound calculated from the lower bound and the declared upper bound is used in calculating the location (processor element and offset) of a particular array element.