Thomas Chen
Veterinary at Drake Rd, Fort Collins, CO

6785870, Aug 31, 2004

Mar 14, 2002

10/098110

Thomas W Chen - Fort Collins CO

Hewlett-Packard Development Company, L.P. - Houston TX

G06F 1750

716 2, 716 5, 716 7

A method of optimizing speed and power consumption of an integrated circuit having at least one path having at least one gate involves creating a parent state representing a partition of the integrated circuit design. Each device in the parent state further has associated device size information and device type information. A population of individual states are created from at least one parent states. These individual states are scored for timing and power dissipation. Survivor individual states of the population are determined based upon scores of each state of the population. The steps of creating the population of individual states, scoring states, and determining survivor states, are iterated as needed. Survivor states are then further optimized with a greedy search, and a best individual survivor state is selected as an optimized state of each partition. The integrated circuit netlist is adjusted to correspond to the optimized state.

6711720, Mar 23, 2004

Mar 14, 2002

10/098136

Thomas W. Chen - Fort Collins CO

Hewlett-Packard Development Company, L.P. - Houston TX

G06F 1750

716 2, 716 4, 716 5, 716 7

A method of optimizing speed and predicted power of integrated circuit designs includes creating a machine representation representing devices of the integrated circuit design, where for each device in a path of the integrated circuit the representation includes device size information and device type information. The device type information includes selection between at least one fast-but-leaky type and at least one slow-but-not-leaky type. A genetic global optimization is then performed, wherein substitutions of both device type and device size are performed to create a population of individual states from at least one parent machine representation in each iteration. Members of the population at each iteration are evaluated for speed and power consumption; and survivor members are selected of the population based upon their scores. Survivor members become parent states of the next iteration; and upon completion of iterations a best survivor is selected, and the integrated circuit netlist is updated to correspond to the best optimized survivor.

6687888, Feb 3, 2004

Mar 14, 2002

10/098111

Thomas W. Chen - Fort Collins CO

Hewlett-Packard Development Company, L.P. - Houston TX

G06F 1750

716 5

A method of optimizing speed and predicted power of integrated circuit designs includes creating a machine representation representing devices of the integrated circuit design, where for each device in a path of the integrated circuit, the representation includes device size information and device type information. The device type information includes selection between at least one fast-but-leaky type and at least one slow-but-not-leaky type. A global optimization is then performed, wherein substitutions of both device type and device size are performed on the machine representation in each iteration. Substituted representations are evaluated for speed and power consumption.

6728941, Apr 27, 2004

Mar 14, 2002

10/098112

Thomas W. Chen - Fort Collins CO

Hewlett-Packard Development Company, L.P. - Fort Collins CO

G06F 945

716 5

A method of calculating a crossover current component of dynamic power dissipation at a gate of a CMOS integrated circuit design is operable on a digital computer. The method includes deriving two constants. An effective width is computed for the gate, a transition time is computed at an input of the gate, an activity ratio is determined for the gate, and a load capacitance is computed at an output of the gate. The effective width is multiplied by the activity ratio, the clock rate, and the difference of the first constant multiplied by the transition time and the second constant multiplied by the load capacitance to determine a crossover current component of dynamic power of the gate.

6858897, Feb 22, 2005

Apr 30, 2003

10/427623

Thomas W. Chen - Fort Collins CO, US

Hewlett-Packard Development Company, L.P. - Houston TX

H01L029/76

257341

An individual-well adaptive method of body bias control that mitigates the effects of D2D and WD process variations is shown. It is assumed that p-type transistors are grouped in sections. The bodies of all the p-type transistors within a section are connected to a single n-well. This section size can be small enough to provide fine-granular adjustments to the circuit without having any impact on area overhead. With a small amount of additional circuitry and routing, individual well biases can be intelligently adjusted resulting in closely controlled chip power and performance. Experimental results show that binning yields as low as 17% can be improved to greater than 90% using the proposed method.

2006005, Mar 16, 2006

Sep 14, 2004

10/940099

Thomas Chen - Fort Collins CO, US
Eugene Berta - Windsor CO, US

G06F 17/50

716006000

One disclosed embodiment may comprise a system that includes design data that describes at least a portion of a circuit design. An analysis system determines timing information for a node associated with a first component of the circuit design relative to variations in a parameter associated with at least one second component of the circuit design. The timing information for the node associated with the first component characterizes a sensitivity of the first component relative to the variations in the parameter associated with the at least one second component.

2005003, Feb 10, 2005

Aug 6, 2003

10/635283

Tyson McGuffin - Fort Collins CO, US
Thomas Chen - Fort Collins CO, US

G06F009/45

716005000

Systems and methods are provided that can be utilized to estimate power associated with a circuit design. The estimated power is determined by evaluating a functional relationship of estimated power based on calculated transistor gate area. One or more power coefficients can be employed with transistor gate area calculations of a circuit design to compute relative power estimates of one or more circuit design sizing instances.

2005028, Dec 29, 2005

Jun 24, 2004

11/089582

Thomas Chen - Fort Collins CO, US
Eugene Berta - Windsor CO, US

G06F009/45

703022000

One disclosed embodiment may comprise a system to facilitate simulation that includes a mapping system that converts parameter data having a first form corresponding to a first frequency distribution for at least one parameter to a second form, the second form corresponding to a modified frequency distribution for the at least one parameter that is functionally related to the first form and that exhibits an increased variation in the at least one parameter relative to the first form.

2005002, Jan 27, 2005

Jul 21, 2003

10/624266

Tyson McGuffin - Fort Collins CO, US
Thomas Chen - Fort Collins CO, US
Dave Anderson - Fort Collins CO, US
David Burden - Fort Collins CO, US

G06F019/00, G01N033/48, G01N033/50

702020000

The convergence speed of a computer-implemented genetic optimization process is improved through the correction of child chromosomes containing undesirable gene combinations. Undesirable gene combinations may be identified through application of heuristic techniques, statistical techniques, or a combination of the two.

2004023, Nov 25, 2004

May 23, 2003

10/445138

Thomas Chen - Fort Collins CO, US

G06G007/54, G06F017/50

703/018000, 716/004000, 716/005000

An indication of power for one or more units of a circuit design are determined based on functional verification data. The functional verification data can be generated for input vectors applied to a representation of the circuit design to functionally verify operation of the design.