Inventors:
Ruiqi Tian - Pflugerville TX, US
Thomas Michael Brown - Austin TX, US
Assignee:
AMD, Inc. - Sunnyvale CA
Motorola, Inc. - Shaumberg IL
International Classification:
H01L021/311
US Classification:
438697, 438626, 438691, 438692, 438129, 438424, 438631, 438645, 438599, 257752, 257750, 257620
Abstract:
In a feature layer of a semiconductor wafer, dummy tiles which overcome the tendency of dishing and erosion to occur during a CMP process are placed with various sizes and in various positions. An isolation zone is provided around active features. A scanning process of the feature layout surveys oxide density and nitride density over the wafer layer outside of said isolation zone. Values of the ratios of oxide/nitride density for two or more length scales which define tiling zones, are calculated. Tile placement and sizing in the zones is dependent upon the oxide/nitride density ratio values; and further upon an oxide deposition model specific to the oxide used in the fabrication process and upon a polishing model of the CMP process being employed.