TAM T NGUYEN
Pharmacy in San Jose, CA

6381181, Apr 30, 2002

Nov 21, 2000

09/718650

Tam Nguyen - San Jose CA

Silicon Storage Technology, Inc. - Sunnyvale CA

G11C 700

36518907, 36518905, 365205

The self-latching data circuit reads data from a pair of memory cells and latches the read data in response to a single transition of an enable signal. The self-latching data circuit includes a pair of PFETS that pull first and second nodes to a power supply voltage in response to an enable signal being in a low state. The self-latching data circuit also includes a pair of series connected PFET and NFETS in which the first and second data nodes are formed of the node connecting the series PFET and NFET together. In response to the enable signal transitioning to a high state, the memory cells are read and the contents thereof are applied to the first and second data nodes. The signal of one data node is applied to the gates of the transistors of the transistor pair corresponding to the other data node. This feedback causes the data cell having the greatest current draw to pull the other data node to the power supply level and pull itself to a zero voltage level to thereby latch the data. In the self-latched condition, the self-latching data circuit has minimal power draw.

6396743, May 28, 2002

May 18, 2001

09/860706

Tam Nguyen - San Jose CA

Silicon Storage Technology, Inc. - Sunnyvale CA

G11C 1606

36518523, 36518505, 36518512, 36518518

A control circuit for a non-volatile memory array having a plurality of sectors, comprises a plurality of mirror circuits connected in parallel. Each mirror circuit comprises a first transistor and a common transistor. The common transistor is common to all of the mirror circuits connected to all of the sectors. A charge pump supplies voltage to the node that connects between the first transistor and the mirror transistor. A current limiter circuit limits the amount of current flowing through the common transistor. The control circuit limits the amount of current that can flow through a defective sector and controls the rate at which voltage from the charge pump is supplied to each of the sectors.

7019394, Mar 28, 2006

Sep 30, 2003

10/674370

Xiaowei Yao - Fremont CA, US
Tam Nguyen - San Jose CA, US
Marc Finot - Palo Alto CA, US
Rickie C. Lake - Sunnyvale CA, US
Jeffrey A. Bennett - Sunnyvale CA, US
Robert Kohler - Zurich, CH

Intel Corporation - Santa Clara CA

H01L 23/053

257700, 257706, 257712

A circuit package includes a base portion and a first metal pattern disposed on a substrate surface. Second and third metal patterns are disposed on another substrate surface, and electrically coupled to first and second vias. The third metal pattern forms a gap to electrically isolate it from the second metal pattern. A circuit package includes a substrate having an opening and a single heat sink positioned in the opening to expose top and bottom surfaces through top and bottom surfaces of the substrate. Selective plating includes applying first and second metal patterns to a substrate surface, creating a potential voltage difference between the first metal pattern and a metal source, and plating the first metal pattern by attracting a first metal type to the voltage potential of the first metal pattern. The voltage potential of the first metal pattern is less than the voltage potential of the metal source.