TAI NGUYEN
Pharmacy at Eldridge Pkwy, Houston, TX

6892266, May 10, 2005

Nov 8, 2001

10/008696

Jay B. Reimer - Houston TX, US
Harland Glenn Hopkins - Missouri City TX, US
Tai H. Nguyen - Houston TX, US
Yi Luo - Stafford TX, US
Kevin A. McGonagle - Sugarland TX, US
Jason A. Jones - Houston TX, US
Duy Q. Nguyen - Austin TX, US
Patrick J. Smith - Houston TX, US

Texas Instruments Incorporated - Dallas TX

G06F013/14

710305, 710308, 710309

A DSP device is disclosed having multiple DMA controllers with global DMA access to all volatile memory resources in the DSP device. In a preferred embodiment, each of the DMA controllers is coupled to each of the memory buses and is configured to control each of the memory buses. A memory bus multiplexer may be coupled between the subsystem memory bus and each of the DMA controllers, and an arbiter may be used to set the memory bus multiplexer so as to allow any one of the DMA controllers to control the memory bus. The memory bus may also be controlled by the host port interface via the memory bus multiplexer. A round-robin arbitration technique is used to provide each of the controllers and the host port interface fair access to the memory bus. This approach may advantageously provide increased flexibility in the use of DMA controllers to transfer data from place to place, with only a minimal increase in complexity.

6609163, Aug 19, 2003

Jun 9, 2000

09/591527

Tai H. Nguyen - Houston TX
Jason A. T. Jones - Houston TX
Jonathan G. Bradley - Houston TX
Natarajan Seshan - Houston TX

Texas Instruments Incorporated - Dallas TX

G06F 300

710 21, 710 14, 710 20, 710 30, 710 33, 710 45, 710 62, 710 72, 709231, 709232, 709236, 712225

A microprocessor is described which includes a multi-channel serial port (MCSP). MCSP includes clock generation and frame sync generation circuitry , multi-channel selection circuitry , and companding circuitry. The clock generation and frame sync generation circuitry is configurable by means of a Serial Port Control Register SPCR, and Receive Control Register RCR, a Transmit Control Register XCR, a Sample Rate Generator Register SRGR, and Pin Control Register PCR. The multi-channel selection circuitry is configurable by means of a Multi-Channel Register MCR, a Receive Channel Enable Register RCER and a Transmit Channel Enable Register XCER. Companding circuitry performs optional expansion or compression of received or transmitted data using -LAW or A-LAW, as selected by the Receive Control Register or the Transmit Control Register.

6895479, May 17, 2005

Nov 8, 2001

10/008515

Jay B. Reimer - Houston TX, US
Tai H. Nguyen - Houston TX, US
Yi Luo - Stafford TX, US
Harland Glenn Hopkins - Missouri City TX, US
Dan K. Bui - Sugarland TX, US
Kevin A. McGonagle - Sugarland TX, US

Texas Instruments Incorporated - Dallas TX

G06F012/14, G06F012/00

711152, 711147, 711150, 711168, 712 35, 709213

A multi-core digital signal processor is disclosed having a shared program memory with conditional write protection. In one embodiment, the digital signal processor includes a shared program memory, an emulation logic module, and multiple processor cores each coupled to the shared program memory by corresponding instruction buses. The emulation logic module preferably determines the operating modes of each of the processors, e. g. , whether they are operating in a normal mode or an emulation mode. In the emulation mode, the emulation logic can alter the states of various processor hardware and the contents of various registers and memory. The instruction buses each include a read/write signal that, while their corresponding processor cores are in normal mode, is maintained in a read state. On the other hand, when the processor cores are in the emulation mode, the processor cores are allowed to determine the state of the instruction bus read/write signals. Each instruction bus read/write signal is preferably generated by a logic gate that prevents the processor core from affecting the read/write signal value in normal mode, but allows the processor core to determine the read/write signal value in emulation mode.