TAE G KIM
Electrician at Northwest Hwy, Dallas, TX

2006000, Jan 12, 2006

Jul 7, 2005

11/175174

Alfred Griffin - Dallas TX, US
Edmund Burke - Dallas TX, US
Asad Haider - Plano TX, US
Kelly Taylor - Allen TX, US
Tae Kim - Dallas TX, US

H01L 21/4763, H01L 21/44

438637000, 438672000, 438644000

Disclosed is a method of fabricating an integrated circuit comprising patterning a dielectric layer to form a hole having a sidewall and a bottom. The hole can expose an underlying material of an electrically conducting material. The method also includes exposing the sidewall and the exposed underlying material to a plasma etch, depositing a barrier layer on the bottom and the sidewall of the hole after the plasma etch clean, forming a counter-sunk cone in the underlying material by etching through the barrier layer at the bottom of the hole into the conducting metal underneath, flash depositing a thin layer of the barrier material into the hole, and finally depositing a metal seed layer in the hole covering the sidewalls and the bottom of the hole including the cone at the bottom. The hole is finally filled by depositing a metal layer in the hole.

2009008, Apr 2, 2009

Sep 28, 2007

11/863448

Zhijian Lu - Boxborough MA, US
Tae S. Kim - Dallas TX, US

TEXAS INSTRUMENTS INCORPORATED - Dallas TX

H01L 21/768, H01L 21/8234, H01L 27/088

257368, 438618, 438275, 257E21627, 257E21575, 257E2706

Fabrication of interconnects in integrated circuits (ICs) use low-k dielectric materials, nitrogen containing dielectric materials, copper metal lines, dual damascene processing and amplified photoresists to build features smaller than 100 nm. Regions of an IC with low via density are subject to nitrogen diffusion from nitrogen containing dielectric materials into low-k dielectric material, and subsequent interference with forming patterns in amplified photoresists, a phenomenon known as resist poisoning, which results in defective interconnects. Attempts to solve this problem cause lower IC circuit performance or higher fabrication process cost and complexity. This invention comprises a dummy via and a method of placing dummy vias in a manner that reduces resist poisoning without impairing circuit performance or increasing fabrication process cost or complexity.

2008015, Jun 26, 2008

Dec 21, 2006

11/614185

Manoj K. Jain - Plano TX, US
Tae S. Kim - Dallas TX, US
Stephan Grunow - Wappingers Falls NY, US

Texas Instruments, Incorporated - Dallas TX

H01L 21/02

438618, 295921

Provided is a method for manufacturing an interconnect. The method for manufacturing the interconnect, in one embodiment, includes forming a first metal feature over or within a substrate, the first metal feature having an exposed surface. The method for manufacturing the interconnect may additionally include cleaning the exposed surface using a reactive system with a reducing agent, and subjecting the exposed surface to a plasma etch. The method for manufacturing the interconnect may further include contacting the first metal feature with a second metal feature.

5342795, Aug 30, 1994

Nov 15, 1993

8/153121

Donald L. Plumton - Dallas TX
Tae S. Kim - Dallas TX

Texas Instruments Incorporated - Dallas TX

H01L 2144

437 40

This is a method of forming a vertical transistor device comprising: forming an n-type first drain/source layer 42; patterning a portion of the first drain/source layer 42 to form a channel 44 and a trench; forming a p-type gate structure 46 in the trench; and forming a n-type second drain/source layer 48 over the gate structure 46 and the channel 44; contacting the gate structure 54; forming p-ohmic contact to the gate structure 56; forming n-ohmic source contact 54; and forming n-ohmic drain contact 58. Other devices and methods are also disclosed.

5610085, Mar 11, 1997

Jun 7, 1995

8/483028

Tae S. Kim - Dallas TX
Donald L. Plumton - Dallas TX

Texas Instruments Incorporated - Dallas TX

H01L 21265

437 29

A vertical field effect transistor (1700) and fabrication method with buried gates (1704) having spaced apart gate fingers and connecting structure and overgrown with source and channel epilayer followed by a doping connection of the gate fingers and connecting structure is disclosed. The vertical field effect transistor elements (1702, 1704, 1706, 1708, 1720, 1724) are made of III-V semiconductor compound grown on a germanium substrate (1726).

7745335, Jun 29, 2010

Dec 21, 2006

11/614511

Changming Jin - Plano TX, US
Sopa Chevacharoenkul - Richardson TX, US
Satyavolu Papa Rao - Garland TX, US
Tae Seung Kim - Dallas TX, US

Texas Instruments Incorporated - Dallas TX

H01L 21/4763, H01L 21/44, B05D 3/00

438687, 438627, 438628, 438660, 438937, 427299

A method of fabricating an interconnect structure, comprising exposing an empty deposition chamber to a process that includes generating reactive species produced from a source gas in the presence of a plasma. The method further comprises terminating the plasma and then introducing a semiconductor substrate with a metal layer thereon into the chamber while the reactive species are present in the chamber.

5468661, Nov 21, 1995

Jun 17, 1993

8/078388

Donald L. Plumton - Dallas TX
Tae S. Kim - Dallas TX

Texas Instruments Incorporated - Dallas TX

H01L 218258

437 40

This is a method of forming a vertical transistor device comprising: forming an n-type first drain/source layer 42; patterning a portion of the first drain/source layer 42 to form a channel 44 and a trench; forming a p-type gate structure 46 in the trench; and forming a n-type second drain/source layer 48 over the gate structure 46 and the channel 44. Other devices and methods are also disclosed.