SUZETTE DENISE VANDIVIER, PA-C
Medical Practice at Elizabeth St, Fort Collins, CO
License number
Colorado PA.0004054
Category
Nursing
Type
Medical
Address
Address
1124 E Elizabeth St, Fort Collins, CO 80524
Phone
(970) 484-0798
(970) 482-0679 (Fax)
(970) 482-0679 (Fax)
Personal information
See more information about SUZETTE DENISE VANDIVIER at radaris.comName
Address
Phone
2807 Whitworth Dr, Fort Collins, CO 80525
614 Hillrose Ct, Fort Collins, CO 80525
614 Hillrose Ct, Fort Collins, CO 80525
2807 Whitworth Dr, Fort Collins, CO 80525
4470 Lemay Ave, Fort Collins, CO 80525
Professional information
See more information about SUZETTE DENISE VANDIVIER at trustoria.com
Serializer/De-Serializer Bus Controller Interface
Serializer/De-Serializer Bus Controller Interface
US Patent:
7610532, Oct 27, 2009
Filed:
Nov 1, 2006
Appl. No.:
11/591158
Inventors:
Aaron Matthew Volz - Fort Collins CO, US
Suzette Denise Vandivier - Fort Collins CO, US
Jeffrey Andrew Slavick - Fort Collins CO, US
Suzette Denise Vandivier - Fort Collins CO, US
Jeffrey Andrew Slavick - Fort Collins CO, US
Assignee:
Avago Technologies General IP (Singapore) Pte. Ltd. - Singapore
International Classification:
G01R 31/28, G11C 29/00, G01R 31/26
US Classification:
714724, 365201, 324765
Abstract:
An application specific integrated circuit (ASIC) uses a dedicated interface between core logic and an independent Serializer/De-serializer bus (SBus) to provide SBus capabilities to the core logic. In addition to the dedicated interface, the ASIC includes a controller responsive to a set of signals and a plurality of receivers distributed about the SBus. Each of the receivers is responsive to a set of commands that can be reused to test logic and support functions across each revision of the ASIC as well as to test separate ASICs with similar arrangements of support functions without requiring the generation of a distinct scan vector to test the ASIC. Additional interfaces, such as an I. E. E. E. 1149. 1 interface, further extend SBus capabilities to external test equipment.
Utilizing Serializer-Deserializer Transmit And Receive Pads For Parallel Scan Test Data
Utilizing Serializer-Deserializer Transmit And Receive Pads For Parallel Scan Test Data
US Patent:
7739567, Jun 15, 2010
Filed:
Feb 26, 2008
Appl. No.:
12/037157
Inventors:
Suzette D. Vandivier - Fort Collins CO, US
Aaron M. Volz - Fort Collins CO, US
Aaron M. Volz - Fort Collins CO, US
Assignee:
Avago Technologies Enterprise IP (Singapore) Pte. Ltd. - Singapore
International Classification:
G01R 31/28
US Classification:
714727, 714724
Abstract:
A Serializer/De-serializer (SerDes) of an integrated circuit (IC) includes selectable inputs and outputs not only for functional data and boundary scan (e. g. , JTAG) test data, but also for parallel-scan test data. The serializing portion of the SerDes includes multiplexing logic responsive to control signals to select or identify one of the multiplexing logic inputs for functional data, boundary scan data and parallel-scan data. The de-serializing portion similarly includes selection logic responsive to such control signals to select or identify one of the selection logic outputs for functional data, boundary scan data and parallel-scan data. The multiplexing logic and selection logic couple the selected input or output, respectively, to the SerDes input/output pads.
Method For Testing Jitter Tolerance Of High Speed Receivers
Method For Testing Jitter Tolerance Of High Speed Receivers
US Patent:
2004020, Oct 14, 2004
Filed:
Apr 9, 2003
Appl. No.:
10/409949
Inventors:
Charles Moore - Loveland CO, US
Aaron Volz - Fort Collins CO, US
Suzette Vandivier - Fort Collins CO, US
Jason Nguyen - Fort Collins CO, US
Aaron Volz - Fort Collins CO, US
Suzette Vandivier - Fort Collins CO, US
Jason Nguyen - Fort Collins CO, US
International Classification:
G06F011/00, G01R031/28
US Classification:
714/728000
Abstract:
A method and apparatus is presented for measuring jitter tolerance in a device under test. A device under test is established to operate at a specific frequency. A bit pattern is generated from a bit pattern generator. The bit pattern generated by the bit pattern generator is produced at a frequency that is a multiple of the frequency that the device under test is operating under. Bits are systematically changed in the bit pattern and then errors are measured in the device under test. As a results the jitter tolerance of the device under test is measured.