SUSAN RISSINGER TEMPEST
Nursing in Poughkeepsie, NY

5173619, Dec 22, 1992

Aug 5, 1991

7/740757

Gene J. Gaudenzi - Purdys NY
Kevin G. Kramer - Wappingers Falls NY
Susan L. Tempest - Poughkeepsie NY

International Business Machines Corporation - Armonk NY

H03K 19177

3072722

A circuit for buffering and parity checking digital data communicated between first and second data buses includes a plurality of bidirectional bit buffer circuits. Each of the bidirection bit buffer circuits includes: a first data path comprising a data receiver, latch, and driver connected in series between the first and second data buses, respectively; a second data path comprising a data receiver, latch and driver connected in series between the second and first data buses, respectively; control mechanisms for controlling the drivers to selectively place the output of the drivers in an active driving or high impedance state; and control mechanisms for controlling the data latches to selectively latch or pass through data. A parity generating circuit is connected at the output of the latch in the first data path of each of the bidirectional bit buffer circuits for generating a parity bit responsive to the data at the output of these latches. A transparent latch and driver circuit with phase splitter are provided for increasing the speed of the circuit without substantially increasing the power requirements.

5107507, Apr 21, 1992

May 26, 1988

7/198961

Patrick M. Bland - Delray Beach FL
Mark E. Dean - Delray Beach FL
Gene J. Gaudenzi - Purdys NY
Kevin G. Kramer - Wappingers Falls NY
Susan L. Tempest - Poughkeepsie NY

International Business Machines - Armonk NY

G06F 1110

371 491

A circuit for buffering and parity checking digital data communicated between first and second data buses includes a plurality of bidirectional bit buffer circuits. Each of the bidirectional bit buffer circuits includes: a first data path comprising a data receiver, latch, and driver connected in series between the first and second data buses, respectively; a second data path comprising a data receiver, latch and driver connected in series between the second and first data buses, respectively; control mechanisms for controlling the drivers to selectively place the output of the drivers in an active driving or high impedance state; and control mechanisms for controlling the data latches to selectively latch or pass through data. A parity generating circuit is connected at the output of the latch in the first data path of each of the bidirectional bit buffer circuits for generating a parity bit responsive to the data at the output of these latches. A transparent latch and driver circuit with phase splitter are provided for increasing the speed of the circuit without substantially increasing the power requirements.

4978927, Dec 18, 1990

Nov 8, 1989

7/433260

Kristen A. Hausman - Delray Beach FL
Gene J. Gaudenzi - Purdys NY
Joseph M. Mosley - Boca Raton FL
Susan L. Tempest - Poughkeepsie NY

International Business Machines Corporation - Armonk NY

H03B 500

331 57

Each section (e. g. , 102) of the ring oscillator consists of three two-input NOR gates; one in the feedforward path (108), one in the feedback path (112), and one in the crossover path (110). The center frequency of the oscillator is controlled by enabling and disabling the appropriate gates, such that a single closed loop path is formed. The gates in the feedforward and crossover paths are directly enabled or disabled (to disable, either input is held high) from a control circuit (FIG. 2). The gates in the feedback path, however, are indirectly enabled and disabled. To enable a particular feedback path gate (e. g. , 118), either the corresponding crossover gate (116) is disabled, or the corresponding feedforward gate is disabled (114) and the crossover gate (122) in the following section is enabled. The later causes the feedback gate (124) in the following section to be disabled, thereby removing the remaining sections (106) of the oscillator from the closed loop path. The NOR gates are implemented as a differential amplifier (FIG.

4810962, Mar 7, 1989

Oct 23, 1987

7/111732

Gene J. Gaudenzi - Purdys NY
Susan L. Tempest - Poughkeepsie NY

International Business Machines Corporation - Armonk NY

G05F 316

323314

A voltage regulator for regulating the voltage at a first node, comprising a first voltage supply; a first node; a first transistor with a control terminal connected to the first node; a circuit for varying the VBE voltage drop of the first transistor in accordance with whether the voltage level of the first voltage supply is above or below a threshold voltage and for continuously sinking current from the first transistor; and a circuit for varying the voltage level at the current-emitting terminal of the first transistor to counteract, in combination with the varying VBE voltage drop, the change in the voltage level of the first voltage supply.