Inventors:
Stewart S. Austin - Morganville NJ
Joseph J. Baldini - Lincroft NJ
Joel E. Jakubson - Neptune NJ
Clarke S. Ryan - Red Bank NJ
Assignee:
AT&T Bell Laboratories - Murray Hill NJ
International Classification:
G06F 1110
Abstract:
Circuitry for detecting errors in a digital bit stream comprising a succession of data blocks and wherein each data block incorporates a parity check. At an error monitoring location, a bistable device toggles in response to either a logical "1" or "0" in the bit stream. The output of the bistable device is sampled at a submultiple of the bit rate and compared with a predetermined criterion to detect bit errors.