STEVEN R PETERSON, PT
Physical Therapy at Mendota Rd, Saint Paul, MN

6472715, Oct 29, 2002

Sep 28, 2000

09/675109

Helmut Puchner - Santa Clara CA
Ruggero Castagnetti - San Jose CA
Weiran Kong - Sunnyvale CA
Lee Phan - Fremont CA
Franklin Duan - Sunnyvale CA
Steven Michael Peterson - Eagan MN

LSI Logic Corporation - Milpitas CA

H01L 2976

257371, 257376, 257387

An integrated circuit structures such as an SRAM construction wherein the soft error rate is reduced comprises an integrated circuit structure formed in a semiconductor substrate, wherein at least one N channel transistor is built in a P well adjacent to one or more deep N wells connected to the high voltage supply and the deep N wells extend from the surface of the substrate down into the substrate to a depth at least equal to that depth at which alpha particle-generated electron-hole pairs can effectively cause a soft error in the SRAM cell. For a 0. 25 m SRAM design having one or more N wells of a conventional depth not exceeding about 0. 5 m, the depth at which alpha particle-generated electron-hole pairs can effectively cause a soft error in the SRAM cell is from 1 to 3 m. The deep N well of the 0. 25 m SRAM design, therefore, extends down from the substrate surface a distance of at least about 1 m, and preferably at least about 2 m.

6642749, Nov 4, 2003

Sep 27, 2002

10/256752

Sifang Wu - Savage MN
Steven M. Peterson - Eagan MN
Mai T. MacLennan - Plymouth MN

LSI Logic Corporation - Milpitas CA

G11C 706

327 55, 327 57

A tri-state sense amplifier is provided, which includes an enable input, a latch and an output driver. The latch has first and second complementary inputs and first and second complementary latch outputs, which are gated by the enable input. The output driver includes a data output, a pull-up transistor coupled to the data output and having a control terminal coupled to the first latch output, and a pull-down transistor coupled to the data output and having a control terminal coupled to the second latch output.

6442061, Aug 27, 2002

Feb 14, 2001

09/783653

Weiran Kong - Sunnyvale CA
Gary K. Giust - Cupertino CA
Ramnath Venkatraman - San Jose CA
Franklin Duan - Sunnyvale CA
Ruggero Castagnetti - Menlo Park CA
Steven M. Peterson - Eagan MN
Myron J. Buer - Shakopee MN
Minh Tien Nguyen - San Jose CA

LSI Logic Corporation - Milpitas CA

G11C 1100

365154, 365188, 365156

A method of forming a memory cell according to the present invention. A first pass gate transistor is formed of a first transistor type. The first pass gate transistor has a gate oxide with a first thickness. The source of the first pass gate transistor is electrically connected to a first bit line, and the drain of the first pass gate transistor is electrically connected to a first state node. The gate of the first pass gate transistor is electrically connected to a memory cell enable line. A second pass gate transistor is also formed of the first transistor type. The second pass gate transistor also has a gate oxide with the first thickness. The source of the second pass gate transistor is electrically connected to a second bit line, and the drain of the second pass gate transistor is electrically connected to a second state node. The gate of the second pass gate transistor is electrically connected to the memory cell enable line. A first state node transistor is also formed of the first transistor type.

6687183, Feb 3, 2004

Nov 27, 2001

09/994517

Steven M. Peterson - Eagan MN
Sifang Wu - Savage MN
Mai Mac Lennan - Plymouth MN
Carl A. Monzel - Lakeville MN

LSI Logic Corporation - Milpitas CA

G11C 800

36523006, 36518905, 36518908

A method for changing the internal timing of a memory to allow adjustment of the access time of the memory to be faster or slower by increasing or decreasing internal margins of the memory (bit line separation), respectively, utilizes the memory compiler for setting the number of core cells used for driving a self time column of the memory.

2004007, Apr 22, 2004

Oct 16, 2002

10/272551

Sifang Wu - Savage MN, US
Steven Peterson - Eagan MN, US
Kevin LeClair - Prior Lake MN, US

G11C029/00

365/200000

A memory having built-in self repair with column shifting is provided. The total single columns are divided into smaller column groups and a bad column group is repaired with a redundant column group. Each column group is multiplexed into a pair of column group bitlines, which are fed into a shift circuit for the column group and a shift circuit for an adjacent column group. The shift circuit for the column group nearest the redundant column group receives the bitlines for that column group and the redundant column group bitlines. If a bad column group is detected, then starting with the column group furthest from the redundant column group, the shift circuit for each column group before the bad column group is deactivated. The shift circuit for the bad column group and the shift circuit for each column group after the bad column group are activated. Therefore, the bad column group is shifted out of the memory and the redundant column group fills the void.