STEVEN PAUL PEKARICH
Pilots at Meadowwood Dr, Rowlett, TX

License number
Texas A1469755
Issued Date
Dec 2015
Expiration Date
Dec 2017
Category
Airmen
Type
Authorized Aircraft Instructor
Address
Address
7309 Meadowwood Dr, Rowlett, TX 75089

Professional information

Steven Pekarich Photo 1

Reconfigurable Chip Level Equalizer Architecture For Multiple Antenna Systems

US Patent:
7561618, Jul 14, 2009
Filed:
Apr 14, 2005
Appl. No.:
11/105755
Inventors:
Steven P. Pekarich - Rowlett TX, US
Timothy M. Schmidl - Dallas TX, US
Aris Papasakellariou - Dallas TX, US
Anand G. Dabak - Plano TX, US
Eko N. Onggosanusi - Allen TX, US
Manish Goel - Plano TX, US
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H03H 7/30
US Classification:
375232
Abstract:
A system comprising a plurality of adaptive equalizers adapted to couple to a plurality of receive antennas, each of the antennas capable of receiving a multipath delay profile estimate (MDPE), control logic interconnecting at least some of the adaptive equalizers, and a control mechanism that, according to different MDPEs, configures at least some of the adaptive equalizers and control logic.


Steven Pekarich Photo 2

Reconfigurable Chip Level Equalizer Architecture

US Patent:
8135057, Mar 13, 2012
Filed:
Nov 3, 2003
Appl. No.:
10/699707
Inventors:
Steven P. Pekarich - Rowlett TX, US
Timothy M. Schmidl - Dallas TX, US
Gibong Jeong - San Diego CA, US
Aris Papasakellariou - Dallas TX, US
Anand G. Dabak - Plano TX, US
Eko N. Onggosanusi - Allen TX, US
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H03H 7/30
US Classification:
375232, 375230, 375231, 375233, 375229, 375347, 375234, 375316, 375349
Abstract:
A reconfigurable chip level equalizer having circuitry that restores signal orthogonality and eliminates channel interference for a wireless transmitted signal. In at least some embodiments, the reconfigurable chip level equalizer comprises two or more adaptive equalizers, a plurality of operational blocks that interconnect the two or more adaptive equalizers, and a control mechanism that configures the two or more adaptive equalizers and operational blocks according to different signal delay profiles.