Steven M Cox
Architects in San Jose, CA

License number
Utah 289213-0301
Category
Architect
Type
Architect
Address
Address
San Jose, CA

Organization information

See more information about Steven M Cox at bizstanding.com

Steven M Cox

San Jose, CA 95112

Categories:
Architects
Phone:
(408) 297-5454 (Phone)


HPC ARCHITECTURE, INC. STEVEN M. COX, A.I.A. ARCHITECT

Santa Clara, CA  -  San Jose, CA

Registration:
Dec 26, 2000
Addresses:
2216 The Alameda, Santa Clara, CA 95050 (Physical)
481 N 1 St, San Jose, CA 95112
State ID:
C2324562
Business type:
Articles of Incorporation
President:
Steven Mark Cox (President)
Agent:
John Pfahnl,San Jose, CA 95113 (Physical)

Professional information

Steven Cox Photo 1

Testing Of Hardware By Using A Hardware System Environment That Mimics A Virtual System Environment

US Patent:
5991529, Nov 23, 1999
Filed:
May 16, 1997
Appl. No.:
8/857154
Inventors:
Steven R. Cox - San Jose CA
Harry M. Chue - Alameda CA
Assignee:
Sony Corporation - Tokyo
Sony Electronics Inc. - Park Ridge NJ
International Classification:
G06F 9455
US Classification:
3955003
Abstract:
A technique for testing a hardware implementation of an integrated circuit design using test algorithms developed for testing a software model of the integrated circuit design. A software model is created for a design of the integrated circuit. The software model is a software algorithm that emulates behavior of the integrated circuit. In addition, a virtual environment for the software model is also constructed. The virtual environment is a software algorithm that emulates an actual environment anticipated for the integrated circuit. Diagnostic tests are performed on the software model while it is operating in the virtual environment. These tests are used to verify and analyze the design for the integrated circuit. Based upon the results of the diagnostic tests, the design is modified as necessary. Once the design for the integrated circuit has been verified by testing the software model, an actual hardware circuit is constructed that implements the software model.


Steven Cox Photo 2

System For Improving Logistics, Tracking And Billing For Worker's Compensation Insurance

US Patent:
7742937, Jun 22, 2010
Filed:
Mar 6, 2002
Appl. No.:
10/091860
Inventors:
Steven R. Cox - San Jose CA, US
Thomas R. Quirk - San Jose CA, US
International Classification:
G06Q 10/00
US Classification:
705 4, 705 2, 705 3
Abstract:
A system for improving worker's compensation programs. Employee presence is detected by using proximity sensors at different places in the workplace. For example, where a company has different workshops, offices, rooms, or other areas, detection of a worker's presence in one or more of the areas allows more accurate information to be used to calculate liabilities such as risk of injury. Data about a worker's presence, duration of presence, repeated presence, or other characteristics of a worker in an area are sensed and logged by a digital system. The system can store and process the data locally, or the data (or a derivative of the data) can be transferred to other entities for storage, processing, analysis or other purposes. For example, the presence data can be sent to insurance providers for calculation of accurate premiums, risk, payouts, etc.


Steven Cox Photo 3

Software Configurable Technique For Prioritizing Interrupts In A Microprocessor-Based System

US Patent:
6081867, Jun 27, 2000
Filed:
May 20, 1998
Appl. No.:
9/082432
Inventors:
Steven R. Cox - San Jose CA
Assignee:
Sony Corporation - Tokyo
Sony Electronics, Inc. - Park Ridge NJ
International Classification:
G06F 946
US Classification:
710264
Abstract:
A software configurable technique for prioritizing and masking interrupts in a microprocessor-based system. Contents of a first plurality of registers map each of a plurality of interrupts to an appropriate one of a second plurality of registers and indicate which interrupts are masked. The second plurality of registers are arranged in a predetermined priority and each contains the starting address of an appropriate interrupt service routine for the corresponding interrupt. The interrupt signals are mapped to the outputs of a plurality of logical "OR" gates according to the contents of the first plurality of registers by a plurality of de-multiplexers coupled to the inputs of the plurality of logical "OR" gates. Each logical "OR" gate corresponds to one of the second plurality of registers. A plurality of logical "AND" gates are coupled to the outputs of the logical "OR" gates so as to allow only the highest priority enabled interrupt signal to enable the corresponding one of the second plurality of registers.