Steven Baeyoung Lee
Engineers at Twin Oaks Dr, Colorado Springs, CO

4910165, Mar 20, 1990

Nov 4, 1988

7/267899

Steven S. Lee - Colorado Springs CO

NCR Corporation - Dayton OH

H01L 2120

437 90

A silicon on insulator fabrication process and structure. The fabrication process includes a reproducible sequence in which an oxide covered substrate is anisotropically etched in the presence of a mask to form trenches which extend into the substrate. Epitaxial silicon is selectively grown in the trench regions in a sucession of first materially doped and thereafter lightly doped layers. The materially doped layer extends above the plane defined by the surface of the substrate. Following a selective removal of the oxide, the materially doped epitaxial layer is exposed at its sidewalls first to an anodization and then to an oxidation ambient. This successive conversion of the materially doped epitaxial layer first to porous silicon and then silicon dioxide dielectric isolates the lightly doped epitaxial layer from the substrate. Planarization of the structure and exposure of the epitaxial surfaces provides electrically isolated islands of monocrystalline silicon for bipolar and field effect device fabrication. A CMOS implementation of the epitaxial islands is readily undertaken by selective counterdoping in the presence of a mask.

4986879, Jan 22, 1991

Mar 19, 1990

7/436567

Steven S. Lee - Colorado Springs CO

NCR Corporation - Dayton OH

B05D 512, H01L 21306

156649

An integrated circuit structure and fabrication process for creating field oxide regions having substantially no bird's beak, a relatively planar concluding surface, substantially no stress induced dislocations at the edges of the active regions, and a substantial absence of notches or grooves at the edges of the active silicon, by a selective combination of material dimensions and process operations. In one form of practicing the invention, the process utilizes a relatively thick pad oxide below the masking nitride layer, and a second, very thin, sidewall masking nitride layer. The thin sidewall masking nitride layer does not utilize an underlying pad oxide layer, but may include a thin underlying screening oxide. Upon oxidation, the thin sidewall nitride is concurrently lifted and converted to oxide, the materials and dimension being selected to ensure that when the field oxide level approaches the level of the thick pad oxide layer stresses at the corners of the active silicon region are relieved through various oxide paths and accentuated oxidation effects.

5447880, Sep 5, 1995

Apr 5, 1994

8/224609

Steven S. Lee - Colorado Springs CO
Kenneth P. Fuchs - Colorado Springs CO
Gayle W. Miller - Colorado Springs CO

AT&T Global Information Solutions Company - Dayton OH
Hyundai Electronics America - Milpitas CA

H01L 2170, H01L 2700

437 60

A method for forming an amorphous silicon programable element which requires less than about one square micron of area. The method includes the steps of forming a bottom conductor, depositing an interlayer dielectric above the bottom conductor, forming a via in the interlayer dielectric, depositing an anti-fuse layer above the bottom conductor within the via, and chemical vapor depositing a conductive plug above the anti-fuse layer and within the via. The method may additionally include the step of chemical vapor depositing a top conductor above the conductive plug.

5904535, May 18, 1999

Nov 13, 1996

8/748969

Steven S. Lee - Colorado Springs CO

Hyundai Electronics America - San Jose CA

H01L21/331

438341

A process for fabricating a bipolar transistor on a silicon-on-insulator substrate which includes etching a bipolar transistor area into the substrate, wherein the bipolar transistor area has substantially vertical sidewalls and a bottom, and forming a buried collector in bottom of the bipolar transistor area. Polysilicon sidewalls are formed adjacent to the vertical sidewalls in the bipolar transistor area, wherein the polysilicon sidewalls are connected to the buried collector. The polysilicon sidewalls are oxidized to form a layer of oxidized polysilicon. Oxide sidewalls are formed on the oxidized polysilicon sidewalls, and epitaxial silicon is formed to fill the bipolar transistor area. A base and an emitter are formed for the bipolar transistor, within the epitaxial barrier.

5728626, Mar 17, 1998

Oct 23, 1995

8/553788

Derryl D. J. Allman - Colorado Springs CO
Steven S. Lee - Colorado Springs CO

AT&T Global Information Solutions Company - Dayton OH
Hyundai Electronics America - San Jose CA
Symbios Logic Inc. - Fort Collins CO

B05D 302, B05D 512, H01L 21445

438608

A method of planarizing a non-planar substrate, such as filling vias and contact holes, spreads a suspension of a conducting material suspended in a liquid on a substrate. The suspension includes an organometallic material, preferably with particles of a polymerized tin or indium alkoxide. The material is spread by spinning the substrate after applying the suspension. The carrier liquid and organic groups are removed by baking and curing at elevated temperatures, thereby depositing the conductive material on the substrate in a layer which is more planar than the substrate and which has regions of greater and lesser thickness. A relatively brief etch step removes conductive material from regions of lesser thickness, leaving material filling vias or contact holes.

6011283, Jan 4, 2000

Oct 19, 1992

7/962544

Steven Lee - Colorado Springs CO
Gayle Miller - Colorado Springs CO

Hyundai Electronics America - Milpitas CA
NCR Corporation - Milpitas CA

H01L 2980, H01L 31112

257273

A monolithic semiconductor device includes a field effect transistor and a bipolar junction transistor with a pillar emitter structure. The pillar structure raises the BJT emitter above the surface of a trenched base. Ions implanted into the base trench diffuses into an extrinsic base contact region. The pillar elevation structure increases travel distance between the trench and the emitter and protects against encroachment without increasing the total emitter area allocated to the BJT device. A spacer oxide adjacent to the pillar separates the pillar from the trench-region implanted with ions.

5557131, Sep 17, 1996

Jul 14, 1994

8/275094

Steven Lee - Colorado Springs CO

AT&T Global Information Solutions Company - Dayton OH
Hyundai Electronics America - San Jose CA
Symbios Logic Inc. - Fort Collins CO

H01L 2976, H01L 21265

257370

A monolithic semiconductor device includes a field effect transistor and a bipolar junction transistor with an elevated emitter structure. An elevation structure raises the BJT emitter above the plane of the base. The elevation structure increases travel distance between a heavily doped base contact region and the emitter and protects against encroachment without increasing the total surface area allocated to the BJT device. A spacer oxide separates the polysilicon base contact and the elevation structure.

5543361, Aug 6, 1996

Dec 8, 1994

8/351843

Steven S. Lee - Colorado Springs CO
Kenneth P. Fuchs - Colorado Springs CO
Gayle W. Miller - Colorado Springs CO

AT&T Global Information Solutions Company - Dayton OH
Hyundai Electronics America - Milpitas CA
Symbios Logic Inc. - Fort Collins CO

H01L 2144

437200

A process for forming a titanium silicide local interconnect between electrodes separated by a dielectric insulator on an integrated circuit. A first layer of titanium is formed on the insulator, and a layer of silicon is formed on the titanium. The silicon layer is masked and etched to form a silicon strip connecting the electrodes, and an overlying second layer of titanium is formed over the silicon strip. The titanium and silicon are heated to form nonsilicidized titanium over a strip of titanium silicide, and the nonsilicidized titanium is removed.

6232649, May 15, 2001

Dec 12, 1994

8/354574

Steven S. Lee - Colorado Springs CO

Hyundai Electronics America - San Jose CA

H01L 27082

257588

A process for fabricating a bipolar transistor on a silicon-on-insulator substrate which includes etching a bipolar transistor area into the substrate, wherein the bipolar transistor area has substantially vertical sidewalls and a bottom, and forming a buried collector in bottom of the bipolar transistor area. Polysilicon sidewalls are formed adjacent to the vertical sidewalls in the bipolar transistor area, wherein the polysilicon sidewalls are connected to the buried collector. The polysilicon sidewalls are oxidized to form a layer of oxidized polysilicon. Oxide sidewalls are formed on the oxidized polysilicon sidewalls, and epitaxial silicon is formed to fill the bipolar transistor area. A base and an emitter are formed for the bipolar transistor, within the epitaxial barrier.