STEPHEN WARD
Broker in Boston, MA

5634041, May 27, 1997

Aug 12, 1992

7/929879

Gill A. Pratt - Wellesley MA
Stephen A. Ward - Chestnut Hill MA

Massachusetts Institute of Technology - Cambridge MA

G06F 112

395553

An interface controlling digital communication between synchronous systems of unequal clock frequency. A phase locked loop generates one clock F. sub. m from the other F. sub. n by locking the phase of the two clocks at a beating period. Within the beating period, a precompiled set of valid and invalid communication clock cycles for each direction of communication are scheduled into lookup tables. The lookup tables generate outputs to a Set of registers for communicating data between the systems of unequal clock frequency.

4700321, Oct 13, 1987

Jul 7, 1986

6/882039

Stephen A. Ward - Chestnut Hill MA

Proconics International, Inc. - Woburn MA

G05B 1918, G06F 1546

364569

Circuitry for providing timing signals spaced in time by a varying amount, the circuitry including calculating means for repetitively performing a calculation to repetitively provide calculation signals the value (SUM) of which varies as a function of the number of times the calculation has been repeated, and timing signal generating means for receiving the calculation signals and providing a series of timing signals spaced in time by varying amounts, a timing signal being generated each time the value (SUM) has changed by a set amount (ACC).

5568361, Oct 22, 1996

Jul 25, 1994

8/279693

Stephen A. Ward - Chestnut Hill MA
Gill A. Pratt - Wellesley MA
John N. Nguyen - Cambridge MA
John S. Pezaris - Cambridge MA

Massachusetts Institute of Technology - Cambridge MA

H05K 700, H05K 702, H01R 2368, H01R 2372

361735

Circuit supporting modules form a three-dimensional communication interconnect mesh. Each module has fewer than six sets of connectors, preferably four. The preferred three-dimensional communication interconnect is a tetrahedral lattice having a regular, isotropic, three-dimensional topology in which each module connects to its four physically closest neighbors. The structure of the tetrahedral interconnect is isomorphic with a diamond lattice structure.

4894770, Jan 16, 1990

Jun 1, 1987

7/057272

Stephen A. Ward - Chestnut Hill MA
Robert C. Zak - Somerville MA

Massachusetts Institute of Technology - Cambridge MA

G11C 700

364200

In a random access memory, a dynamic memory array is associated with static data buffers. Each static data buffer is connected to the memory array to receive and store a row of data from any addressed row of the array. When an address is received, it is compared with addresses stored in registers and associated with the data stored in the static buffers. Where there is a match, a controller is able to select the data buffer in which the row of data is stored for a column strobe operation without the need for a row address strobe operation. The resultant system provides for a set associative cache coupled to the dynamic memory array. Further, the comparison can be made of virtual addresses for a cache system which responds to virtual addresses.