STEPHEN T POMFRET
Real Estate Appraisers in Maynard, MA
License number
Massachusetts 2895
Issued Date
May 4, 1993
Expiration Date
Nov 27, 1999
Type
Real Estate Appraiser Trainee
Address
Address
Maynard, MA 01754
Professional information
Computer Interconnect System With Transmit-Abort Function
US Patent:
5020020, May 28, 1991
Filed:
Apr 7, 1989
Appl. No.:
7/335130
Inventors:
Stephen T. Pomfret - Maynard MA
Richard Lary - Colorado Springs CO
Yerell Boaen - Grofon MA
Richard Lary - Colorado Springs CO
Yerell Boaen - Grofon MA
Assignee:
Digital Equipment Corporation - Maynard MA
International Classification:
G06F 1314, H04L 1256
US Classification:
364900
Abstract:
A computer interconnect system uses packet data transmission over serial links connecting nodes of a network. The serial links may provide simultaneous dual paths for transmit/receive. An adapter couples a CPU or the like at a node to the serial link. The adapter includes a packet memory for temporarily storing transmit packets and receive packets, along with a port processor for executing the protocol. Packets of data are transferred between the system bus of the CPU and the packet memory by a pair of data movers, one for read and one for write. All of the serial links of the system are connected to a distribution hub which forwards a transmitted packet to a destination node based upon an address sent with the packet. If the path to the destination node is busy, the hub returns a "flow control" signal to the source node, and in response to this signal the transmitted packet is aborted so that time on the network is not wasted by needless transmission that must be discarded.
Bus For Data Processing System With Fault Cycle Operation
US Patent:
4543628, Sep 24, 1985
Filed:
Jan 28, 1983
Appl. No.:
6/461838
Inventors:
Stephen T. Pomfret - Maynard MA
Assignee:
Digital Equipment Corporation - Maynard MA
International Classification:
G06F 1300, G06F 1100
US Classification:
364200
Abstract:
A digital data processing system including a number of input/output units that communicate with a memory over an input/output bus and through an input/output interface. The input/output interface pipelines data transfers between the input/output units and the memory. The interface includes an incoming and outgoing buffer for queuing requests from the input/output units, and transfers from the memory. In the event of an error in the input/output interface's pipeline buffer, the interface transmits, by means of a fault cycle over the bus, information to the input/output unit that initiated the transfer unit to enable it to recover.