STEPHEN SMITH
Geologists at Southern Ave, Tempe, AZ

4289982, Sep 15, 1981

Jun 28, 1979

6/053148

Stephen L. Smith - Tempe AZ

Motorola, Inc. - Schaumburg IL

H03K 19173, H03K 19096, G11C 700, G11C 1140

307463

An insulated-gate field-effect-transistor (IGFET) quasi-static decoder for programming an electronically-programmable read-only memory (EPROM) applies to the floating gate of selected memory devices a programming voltage. Prior to selection, each row and column conductor of the memory is latched at a first voltage. Precharge circuitry responsive to a single precharge pulse establishes an enabling voltage for unlatching a selected row and column. The selected row and column is then coupled via a switch to a source of programming voltage.

4689504, Aug 25, 1987

Dec 20, 1985

6/811227

Kuppuswamy Raghunathan - Austin TX
Jeffrey R. Jorvig - Chandler AZ
Stephen L. Smith - Tempe AZ

Motorola, Inc. - Schaumburg IL

G11C 8000, H03K 19092, H03K 17687

307449

A high voltage CMOS decoder and level translator for use in conjunction with EPROMS and EEPROMS utilizes additional series coupled field effect transistors maintained in an on condition so a to prevent the voltage across the pull-up and pull-down field effect transistors from exceeding their break down voltages. For example, in addition to a pull-up P-channel field effect transistor and a pull-down N-channel field effect transistor in the output inverter circuit, additional P-channel and N-channel field effect transistors are coupled in series between the pull-up and pull-down transistors to maintain the voltage across the pull-up and pull-down transistors from exceeding there breakdown voltages.

4968903, Nov 6, 1990

Aug 3, 1989

7/389202

Stephen L. Smith - Tempe AZ
Dean Mueller - Chandler AZ

Motorola Inc. - Schaumburg IL

H03K 19173

307469

A combinational static CMOS logic circuit for providing a plurality of basic two-input logic functions with reduced complexity and integrated circuit area. The combinational static CMOS logic circuit provides either a NAND or an XOR output at a first output terminal and a NOR output at a second output terminal. A configuration input terminal is utilized for selecting between the NAND or the XOR output being provided at the first output terminal. In an alternate configuration, the combinational static CMOS logic circuit provides either a NOR or an XNOR output at a first output terminal and a NAND output at a second output terminal.

4267501, May 12, 1981

Jun 21, 1979

6/050729

Stephen L. Smith - Tempe AZ

Motorola, Inc. - Schaumburg IL

G05F 156

323313

An NMOS voltage regulator circuit generates a reference voltage for comparison with, for example, TTL logic levels. A resistive voltage divider coupled to a 5 volt source produces a voltage of, for example, 1. 5 volts which is applied to the non-inverting input of a differential amplifier. The reference voltage appears at the inverting input of the differential amplifier. Field effect transistor means are provided to raise or lower the voltage at the inverting input depending on whether a negative or positive excursion has taken place.

4237547, Dec 2, 1980

Sep 17, 1979

6/075928

Stephen L. Smith - Tempe AZ

Motorola, Inc. - Schaumburg IL

G11C 1140

365189

In a shared contact electrically programmable read only memory, decoding circuitry is provided to prevent unwanted device programming due to sneak paths to ground. A two input NAND gate is coupled between adjacent column select lines. If either of the adjacent column select lines are energized, a data line will be enabled. Thus, for each column line energized, only two data lines will be enabled and only one of these will carry a voltage for enabling a memory device.

4464736, Aug 7, 1984

Sep 23, 1982

6/421748

Stephen L. Smith - Tempe AZ

Motorola, Inc. - Schaumburg IL

G11C 1140, G11C 1300

365200

An E. sup. 2 PROM redundant memory element is provided whereby faulty or improperly coded ROM or E. sup. 2 PROM elements may be replaced by the user in-package. An address programming element including an E. sup. 2 PROM floating gate device having a programmed mode, an unprogrammed mode, and an inhibit mode, may be programmed and erased in-package. Addresses received by the redundant memory element in addition to other inputs determine the mode of the floating gate device.