Stephen Bradford Smith
Engineers at Alamosa Dr, Chandler, AZ

5553012, Sep 3, 1996

Mar 10, 1995

8/401515

John M. Buss - Tempe AZ
James D. Dworkin - Chandler AZ
Scott E. Lloyd - Hoffman Estates IL
Shao W. Pan - Schaumburg IL
Stephen L. Smith - Chandler AZ

Motorola, Inc. - Schaumburg IL

G06F 102, G06F 700, G06F 1500, H03M 750

364722

A circuit and method for computing an exponential signal x. sup. g is provided. The circuit includes a logarithm converter which converts an input signal to binary word that represents the logarithm of an input signal x. A first shift register shifts the binary word in a bit-wise fashion to produce a first intermediate value; while a second shift register shifts the binary word in a bit-wise fashion to produce a second intermediate value. The shift registers may be implemented using multiplexers. The shifting operations are equivalent to multiplying the intermediate values by a factor which is a power of two. The first intermediate value is either added to or subtracted from the second intermediate value to produce a combined value. An inverse-logarithm converter converts the combined value to the exponential signal.

5608663, Mar 4, 1997

Mar 3, 1995

8/398273

Stephen L. Smith - Chandler AZ

Motorola, Inc. - Schaumburg IL

G06F 1711

3647485

A computational array circuit (100) performs parallel multiplications with an adder array (140). The computational array circuit converts a floating point input value to a logarithmic input value. The logarithmic input value is then added to a logarithm of a multiplier value by an adder circuit (145) in each of a number of array elements (150) of the adder array (140). The computational array circuit (100) converts the resulting logarithmic output value from each of the array elements (150) to an antilogarithmic output value. The antilogarithmic output value from each of the array elements is thus the mathematical equivalent of the floating point input value multiplied by the multiplier value. The computational array circuit (100) thus obtains the advantage of floating point precision and range while requiring far less physical area than floating point multipliers would require to perform the same functions.

5726924, Mar 10, 1998

Jul 11, 1996

8/680282

John Michael Buss - Tempe AZ
James Douglas Dworkin - Chandler AZ
Scott Edward Lloyd - Hoffman Estates IL
ShaoWei Pan - Schaumburg IL
Stephen L. Smith - Chandler AZ

Motorola Inc. - Schaumburg IL

G06F 102, G06F 700, G06F 1500, G06F 750

364722

A circuit and method for computing an exponential signal x. sup. g is provided. The circuit includes a logarithm converter which converts an input signal to binary word that represents the logarithm of an input signal x. A first shift register shifts the binary word in a bit-wise fashion to produce a first intermediate value; while a second shift register shifts the binary word in a bit-wise fashion to produce a second intermediate value. The shift registers may be implemented using multiplexers. The shifting operations are equivalent to multiplying the intermediate values by a factor which is a power of two. The first intermediate value is either added to or subtracted from the second intermediate value to produce a combined value. An inverse-logarithm converter converts the combined value to the exponential signal.

5752012, May 12, 1998

Mar 4, 1996

8/610775

Stephen Lee Smith - Chandler AZ

Motorola - Schaumburg IL

G06F 104

395559

A computational array includes a self timed computational element that performs self timed calculations internally independent of a global clock. The self timed computational element includes a computational unit (100) which produces a complete signal upon the completion of calculation of a result value. The self timed computational element also includes a self timed control unit (200) which determines whether a new result value is to be calculated by the computational unit (100) based on an iteration signal which indicates a number of times the new result value is to be calculated, and based on the complete signal received from the computational unit (100) indicating that each previous calculation has been completed. Upon determining that a new result value is to be calculated, the self timed control unit (200) provides a self timed clock signal to the computational unit (100) and the computational unit (100) calculates the new result value accordingly.

5600581, Feb 4, 1997

Feb 22, 1995

8/391880

James D. Dworkin - Chandler AZ
Philip B. Giangarra - Mansfield MA
Stephen L. Smith - Chandler AZ

Motorola, Inc. - Schaumburg IL

G06F 102, G06F 700, G06F 1500

364722

A converter which may be used for implementing either logarithmic or inverse-logarithmic functions includes a memory, a multiplier, and an adder. The memory stores a plurality of pre-computed values which are used in an interpolation to estimate a logarithmic or inverse-logarithmic function over a domain of input signals.

5852730, Dec 22, 1998

Dec 12, 1996

8/764429

John Michael Buss - Tempe AZ
James Douglas Dworkin - Chandler AZ
Stephen Lee Smith - Chandler AZ

G06F 940

395588

A programmable versatile digital signal processing system architecture (FIG. 5) allows the implementation of functions for transmitting and receiving a variety of narrow and wide-band communication signaling schemes. The flexibility of the architecture (FIG. 5) makes it possible to receive and transmit many different spectral communication signals in real time by implementing signal processing functions such as filtering, spreading, de-spreading, rake filtering, and equalization under the direction of program instructions (1300, 1400, 1500, 1600).

6259720, Jul 10, 2001

Dec 12, 1996

8/764344

John Michael Buss - Tempe AZ
James Douglas Dworkin - Chandler AZ
Stephen Lee Smith - Chandler AZ

Motorola, Inc. - Schaumburg IL

H04B 169

375130

A programmable versatile digital signal processing system architecture (FIG. 5) allows the implementation of functions for transmitting and receiving a variety of narrow and wide-band communication signaling schemes. The flexibility of the architecture (FIG. 5) makes it possible to receive and transmit many different spectral communication signals in real time by implementing signal processing functions such as filtering, spreading, de-spreading, rake filtering, and equalization under the direction of program instructions (FIGS. 13, 14, 15, and 16).