Stephen B. Johnson
Electrician at Pembroke St, Colorado Springs, CO

License number
Colorado 8669
Issued Date
Jul 18, 1986
Renew Date
Feb 28, 1989
Expiration Date
Feb 28, 1989
Type
Journeyman Electrician
Address
Address
3706 Pembroke St, Colorado Springs, CO 80907

Personal information

See more information about Stephen B. Johnson at radaris.com
Name
Address
Phone
Stephen Johnson, age 67
4770 Daybreak Cir, Colorado Spgs, CO 80917
(719) 337-6587
Stephen Johnson
482 32 1/8 Rd APT 1, Clifton, CO 81520
(970) 631-3083
Stephen Johnson
514 S Howes St, Fort Collins, CO 80521

Professional information

Stephen Johnson Photo 1

Sr Mgr It Operations And Maintenance

Position:
Operations and Maintenance Manager at Boecore
Location:
Colorado Springs, Colorado Area
Industry:
Information Technology and Services
Work:
Boecore since Oct 2005 - Operations and Maintenance Manager Qwest Communications 1997 - 2005 - Staff IT Network Engineer Allied Signal Technical Services 1996 - 1997 - Senior Network Engineer Imperial Sugar 1995 - 1996 - Senior Support Engineer U.S. Air Force Feb 1987 - Jun 1995 - Satellite Operations Officer
Education:
Colorado Technical University Jan 1993 - Mar 1996
Master of Science, Computer Science
Oregon State University Sep 1982 - Jun 1986
Bachelor of Science, Computer Science


Stephen Johnson Photo 2

Single Chip Protocol Engine And Data Formatter Apparatus For Off Chip Host Memory To Local Memory Transfer And Conversion

US Patent:
6185620, Feb 6, 2001
Filed:
Apr 3, 1998
Appl. No.:
9/054849
Inventors:
David M. Weber - Monument CO
Timothy E. Hoglund - Colorado Springs CO
Stephen M. Johnson - Colorado Springs CO
John M. Adams - Colorado Springs CO
Mark A. Reber - Alpharetta GA
Assignee:
LSI Logic Corporation
International Classification:
G06F 1100, G06F 946, H04Q 1104
US Classification:
709230
Abstract:
A method and apparatus for transferring data from a host to a node through a fabric connecting the host to the node. A chip architecture is provided in which a protocol engine provides for on ship processing in transferring data such that frequent interrupts from various components within the chip may be processed without intervention from the host processor. Additionally, context managers are provided to transmit and receive data. The protocol engine creates a list of transmit activities, which is traversed by the context managers, which in turn execute the listed activity in a fashion independent from the protocol engine. In receiving data, the context managers provide a mechanism to process frames of data originating from various sources without requiring intervention from the protocol engine. When receiving data, the context managers are able to process frames from different sources, which arrive out of order. Additionally, the context managers also determine when all frames within a sequence have been received.


Stephen Johnson Photo 3

Method Of Responding To I/O Request And Associated Reply Descriptor

US Patent:
6591310, Jul 8, 2003
Filed:
May 11, 2000
Appl. No.:
09/569715
Inventors:
Stephen B. Johnson - Colorado Springs CO
Assignee:
LSI Logic Corporation - Milpitas CA
International Classification:
G06F 1314
US Classification:
710 3, 710 5, 710 33, 710 48
Abstract:
A reply descriptor for transmission over an I/O message passing medium in response to a corresponding request message, the descriptor comprises at least one indication field that can function as a ‘flag’ to identify its type, and a content field; whereby a reply message is generated only if at least one predefined condition is not met and the content field will, accordingly, comprise information of that reply messages storage location. The content field to comprise data copied from the I/O request message if each predefined condition is met. A method of responding over an I/O message passing medium to a request message comprising the steps of: generating a reply message to the request message only if at least one predefined condition is not met; generating a reply descriptor having at least one indication field and a content field; whereby the content field comprises information of the reply messages storage location if so generated. Also, a program code on a computer readable storage medium comprising: a first program sub-code for generating a reply message to a corresponding I/O request message only if at least one predefined condition is not met. The first program sub-code comprising instructions for generating a reply descriptor having at least one indication field and a content field that comprises information of the reply messages storage location if said reply message is so generated.


Stephen Johnson Photo 4

Back-Off Retry With Priority Routing

US Patent:
2011011, May 12, 2011
Filed:
Jan 18, 2011
Appl. No.:
13/008706
Inventors:
Stephen B. Johnson - Colorado Springs CO, US
Christopher McCarty - Colorado Springs CO, US
Wiliam Petty - Colorado Springs CO, US
Jeffrey J. Gauvin - Manitou Springs CO, US
Assignee:
LSI CORPORATION - Milpitas CA
International Classification:
G06F 13/00
US Classification:
710300
Abstract:
A method for back-off retry with priority routing in a single, cohesive SAS expander includes routing a data transfer between an input of a single, cohesive SAS expander and an output of the single, cohesive SAS expander, wherein the single, cohesive expander includes a first SAS expander, and at least one additional SAS expander via at least one inter-expander link (IEL). The routing of data may further include routing a first OPEN request on a direct path through the first SAS expander to a port of a device and routing a second OPEN request on an alternate path from the first SAS expander and through a second SAS expander to the port of the device. The method further includes determining link availability between the second SAS expander and the port of the device, and, upon determination of a failed link or a busy link, re-routing the data transfer from the second SAS expander to the first SAS expander or a third SAS expander, or retrying the data transfer through the second SAS expander.


Stephen Johnson Photo 5

Method And Apparatus For Embedding Configuration Data

US Patent:
7007036, Feb 28, 2006
Filed:
Mar 28, 2002
Appl. No.:
10/109285
Inventors:
Christopher J. McCarty - Colorado Springs CO, US
Stephen B. Johnson - Colorado Springs CO, US
Brad D. Besmer - Colorado Springs CO, US
Assignee:
LSI Logic Corporation - Milpitas CA
International Classification:
G06F 7/00
US Classification:
707102, 707 1, 711114
Abstract:
The present invention provides an apparatus and a method for embedding information from a first configuration data set having data structures into an embedded processing system, wherein embedding the information maintains user-defined variables. Embedding information includes comparing a first identifier from the first configuration data set with a second identifier from a second configuration data set having data structures to determine if the first identifier differs from the second identifier. In response to a determination of the first identifier differing from the second identifier, a decision is made to merge the first configuration data set with the second configuration data set to form a merged configuration data set. Afterwards, the merged configuration data set is written to the embedded processing system, wherein the merged configuration data set includes maintained user-defined variables.


Stephen Johnson Photo 6

Methods And Systems For Load Balancing Of Virtual Machines In Clustered Processors Using Storage Related Load Information

US Patent:
7444459, Oct 28, 2008
Filed:
Dec 12, 2006
Appl. No.:
11/609408
Inventors:
Stephen B. Johnson - Colorado Springs CO, US
Assignee:
LSI Logic Corporation - Milpitas CA
International Classification:
G06F 12/00
US Classification:
711 6, 711154, 711165, 718105
Abstract:
Methods and systems for generating storage related load factor information for load balancing of multiple virtual machines operable in a cluster of multiple physical processors (such as a blade center). Load factor information is generated within a storage system relating to operation of the storage system as a whole and relating to each of multiple storage controllers in the storage system. The information so generated in the storage system is communicated to a load balancing element associated with the multiple virtual machines. The load balancing element then utilizes the storage related load factor information, optionally in combination with other load factor information, to distribute or redistribute the operation of the multiple virtual machines over the plurality of physical processors.


Stephen Johnson Photo 7

Method And System For Combining Multiple Serial Attached Small Computer System Interface (Sas) Expanders

US Patent:
7849248, Dec 7, 2010
Filed:
Apr 2, 2009
Appl. No.:
12/384289
Inventors:
Stephen B. Johnson - Colorado Springs CO, US
Timothy E. Hoglund - Colorado Springs CO, US
Assignee:
LSI Corporation - Milpitas CA
International Classification:
G06F 13/00
US Classification:
710300, 710 2, 710 3
Abstract:
At least one first numbered phy of a first SAS expander is grouped with at least one second numbered phy of a second SAS expander physically separate from the first SAS expander into at least one common SAS wide port. An identical SAS address is assigned to the first SAS expander and the second SAS expander for operating the first SAS expander and the second SAS expander to behave and respond as a single, cohesive SAS expander. The first SAS expander is directly connected to the second SAS expander for inter-expander communications.


Stephen Johnson Photo 8

Method And System For Combining Multiple Sas Expanders Into A Sas Switch

US Patent:
8244948, Aug 14, 2012
Filed:
Jun 1, 2010
Appl. No.:
12/791244
Inventors:
Stephen B. Johnson - Colorado Springs CO, US
Christopher McCarty - Colorado Springs CO, US
Assignee:
LSI Corporation - Milpitas CA
International Classification:
G06F 13/00
US Classification:
710300, 710309, 710311, 710312
Abstract:
A first SAS expander including at least phys is operably coupled to a first and a second SAS wide port. A second SAS expander including at least two phys is operably coupled to the first and the second SAS wide port. The first and the second SAS wide port each include at least two lanes, one of each at least two lanes designateable as a connection request lane. The connection request lane of each SAS wide port is operably coupled to a different SAS expander.


Stephen Johnson Photo 9

Method And System For Creating And Utilizing Virtual Hardware Resources

US Patent:
2008004, Feb 14, 2008
Filed:
Aug 14, 2006
Appl. No.:
11/504190
Inventors:
Ming-jen Wang - Colorado Springs CO, US
Stephen Johnson - Colorado Springs CO, US
Owen Parry - Colorado Springs CO, US
Bradley Dean Besmer - Colorado Springs CO, US
International Classification:
G06F 9/46
US Classification:
718104
Abstract:
A data-processing method and system generally comprises identifying a plurality of hardware resources associated with a data-processing apparatus, time-slicing the plurality of hardware resources. Thereafter the plurality of active hardware resources can be allocated among a plurality of active hardware resources associated with the data-processing apparatus, thereby allowing a limited number of hardware resources to service a larger number of physical devices associated with the data-processing apparatus. An appropriate hardware resource can be selected from among the plurality of active hardware resources utilizing one or more swapping algorithms.


Stephen Johnson Photo 10

Stephen Johnson

Location:
Colorado Springs, Colorado Area
Industry:
Higher Education