STEPHEN ANDREW BOWLING
Pilots at Kempton Rd, Chandler, AZ

2003006, Mar 27, 2003

Jun 1, 2001

09/870457

Michael Catherwood - Pepperell MA, US
Brian Boles - Mesa AZ, US
Stephen Bowling - Chandler AZ, US
Joshua Conner - Apache Junction AZ, US
Rodney Drake - Mesa AZ, US
John Elliot - Chandler AZ, US
Brian Fall - Chandler AZ, US
James Grosbach - Scottsdale AZ, US
Tracy Kuhrt - Mesa AZ, US
Guy McCarthy - Chandler AZ, US
Manuel Muro - Chandler AZ, US
Michael Pyska - Phoenix AZ, US
Joseph Triece - Phoenix AZ, US

G06F015/00

712/035000

An instruction set is provided that features ninety four instructions and various address modes to deliver a mixture of flexible micro-controller like instructions and specialized digital signal processor (DSP) instructions that execute from a single instruction stream.

6552625, Apr 22, 2003

Jun 1, 2001

09/870650

Stephen A. Bowling - Chandler AZ

Microchip Technology Inc. - Chandler AZ

H03K 0708

332109, 327172, 327175

A processor that has pulse width modulation generation circuitry that provides an improved capability to deal with fault conditions, and particularly with multiple concurrent fault conditions, occurring in external circuitry and devices that are connected to PWM hardware included in a processor. A pulse width modulation generator for a processor includes fault priority circuitry having a plurality of fault inputs operable to receive fault input signals and a fault output operable to output a fault output signal, the fault priority circuitry operable to receive fault input signals on a plurality of fault inputs concurrently, and output a fault output signal corresponding to a fault input having a highest priority among the fault inputs that are receiving fault input signals, and pulse width modulation circuitry having at least one pulse width modulation output operable to output at least one pulse width modulated signal and a fault input operable to receive the fault output signal from the fault priority circuitry, the pulse width modulation circuitry operable to drive the pulse width modulation output to a defined state associated with the selected fault input.

6552567, Apr 22, 2003

Sep 28, 2001

09/964664

Brian Boles - Mesa AZ
Richard Fischer - Mesa AZ
Sumit Mitra - Tempe AZ
Rodney Drake - Mesa AZ
Stephen A. Bowling - Chandler AZ
Bryan Kris - Chandler AZ
Steven Marsh - Phoenix AZ
Hassan Harb - Gilbert AZ

Microchip Technology Incorporated - Chandler AZ

H03K 190175

326 63, 327333

The present invention relates generally to functional pathway configurations at the interfaces between integrated circuits (ICs) and the circuit assemblies with which the ICs communicate. More particularly, the present invention relates generally to the functional pathway configuration at the interface between one or more semiconductor integrated circuit dice, including an IC package and the circuitry of a system wherein the integrated circuit dice is a digital signal controller. Even more particularly, the present invention relates to a 18, 28, 40, 44, 64 or 80 pin functional pathway configuration for the interface between the digital signal controller and the system in which it is embedded.

7642735, Jan 5, 2010

Sep 5, 2006

11/470052

John K. Gulsen - Aliso Viejo CA, US
Stephen Bowling - Chandler AZ, US

Microchip Technology Incorporated - Chandler AZ

H05B 37/02, H05B 41/36

315360, 315307

Pulse Density Modulation (PDM) is used to control the amount of light from a fluorescent lamp by applying a voltage to the lamp filaments at a low frequency that is approximately at a series resonant frequency of the lamp ballast inductor and the lamp filament capacitor, no voltage and a voltage at a high frequency. The lamp gas ionizes to produce light only when the low frequency voltage is applied. The fluorescent lamp gas does not ionize when the voltage at the high frequency is applied, but the high frequency voltage keeps the lamp filaments warm during low light output conditions. The low frequency, no and high frequency voltages have time periods that occur within a modulation frame time period that repeats continuously. The ratio of the low frequency voltage time period, and the no voltage and/or high frequency voltage time periods determine the light output of the fluorescent lamp.

2003000, Jan 2, 2003

Jun 1, 2001

09/870462

Joseph Triece - Phoenix AZ, US
Michael Pyska - Phoenix AZ, US
Stephen Bowling - Chandler AZ, US
Michael Catherwood - Pepperell MA, US

G06F012/00

711/200000, 711/168000

A processor has a native word width of multiples of a byte width. The processor may, nonetheless, process, store and retrieve data in word or byte widths depending on the mode of an instruction directing the processing. Instructions may assume either a word or a byte mode. In the word mode, the instruction causes the processor to read, store and operate on word width data. In the byte mode, the instruction causes the processor to read, store and operate on byte data where the byte is specified based on upper/lower byte bits in the instruction. This architecture permits a new generation of processor having word widths of more than one byte to be backward compatible with software written for byte width processors.

2002019, Dec 19, 2002

Jun 1, 2001

09/870455

Stephen Bowling - Chandler AZ, US

H03K003/017

327/175000

An extended resolution mode for a PWM generator is provided. The extended resolution mode takes advantage of the higher frequency Q clock generation scheme on processors that include the PWM generator. Specifically, a Q clock counter, which operates at four times the frequency of the oscillator fed into the rest of the PWM generator, is used to generate a two bit output. This two bit output is used as the lower order bits of an n-bit period counter of the PWM generator during a high resolution mode to generate PWM signal edges. The two upper bits of the n-bit period counter are ignored during PWM signal edge generation in high resolution mode. The high resolution mode greatly improves PWM signal control at low frequencies of operation. During a normal resolution mode, the Q clock counter is ignored during PWM signal edge generation.

2005016, Jul 28, 2005

Oct 19, 2004

10/969338

Michael Catherwood - Pepperell MA, US
Edward Boles - Mesa AZ, US
Stephen Bowling - Chandler AZ, US
Joshua Conner - Apache Junction AZ, US
Rodney Drake - Gilbert AZ, US
John Elliott - Chandler AZ, US
Brian Fall - Chandler AZ, US
James Grosbach - Scottsdale AZ, US
Tracy Kuhrt - Apache Junction AZ, US
Guy McCarthy - Chandler AZ, US
Manuel Muro - Cary NC, US
Mike Pyska - Phoenix AZ, US
Joseph Triece - Phoenix AZ, US

G06F015/00

712034000

An instruction set is provided that features multiple instructions and various address modes to deliver a mixture of flexible microcontroller-like instructions and specialized digital signal processing (“DSP”) execute instructions from a single instruction stream. A subset of instructions of the instruction set can be executed by a processor. Similarly, another subset of the instructions can be utilized by the digital signal processor. A software application can thus take advantage of digital signal processing capabilities in the same program, obviating the need for separate programs for separate processors.

7804379, Sep 28, 2010

May 7, 2008

12/116468

Bryan Kris - Phoenix AZ, US
Stephen Bowling - Chandler AZ, US

Microchip Technology Incorporated - Chandler AZ

H02M 1/12, H02M 3/335, H03K 7/08

332109, 332110, 363 26, 363 41

Dead time compensated complementary pulse width modulation (PWM) signals are derived from a PWM generator by first applying time period compensation to the PWM generator signal based upon the direction of current flow in an inductive load being controlled by the PWM generator. Dead time is then applied to the compensated PWM generator signal for producing complementary dead time compensated PWM signals for controlling power switching circuits driving the inductive load.

2013019, Aug 1, 2013

Jan 29, 2013

13/753375

Microchip Technology Incorporated - Chandler AZ, US
Stephen Bowling - Chandler AZ, US

MICROCHIP TECHNOLOGY INCORPORATED - Chandler AZ

G06F 1/24

713 1

A microcontroller has a plurality of peripherals, and at least one control bit, wherein the control bit controls a reset of at least one peripheral such that in a first mode any type of reset resets the at least one peripheral of said plurality of peripherals and in a second mode only a power supply reset resets the at least one peripheral.

2013008, Mar 28, 2013

Sep 28, 2011

13/247489

Stephen Bowling - Chandler AZ, US
Igor Wojewoda - Tempe AZ, US

G06F 1/14

713502

A microcontroller has a central processing unit (CPU), a plurality of peripherals, and a programmable scheduler unit with: a timer being clocked by an independent clock signal; a comparator coupled with a timer register of said timer and having an output generating an output signal; an event register coupled with said comparator; a delta time register; and an arithmetic logic unit controlled by the output signal of the comparator and with first and second inputs and an output, wherein the first input is coupled with the timer register or the event register and the second input is coupled with the delta time register and the output is coupled with the event register.