STEPHEN ALAN TURK
Pilots at Monarch Ave, Longmont, CO

6505320, Jan 7, 2003

Mar 9, 2000

09/521554

Stephen A. Turk - Longmont CO
Christopher P. Zook - Longmont CO
Marvin L. Vis - Longmont CO

Cirrus Logic, Incorporated - Austin TX

H03M 1329

714755, 341 59, 714769

A sampled amplitude read channel is disclosed for writing data to and reading data from a disk storage medium. A first channel encoder encodes a first j-k bits of a j-bit data block to generate first encoded data, and an ECC encoder encodes the first encoded data and a remaining k-bits of the data block to generate ECC redundancy symbols comprising a plurality of bits. A second channel encoder encodes the remaining k-bits of the data block and the ECC redundancy symbols to generate second encoded data. The first encoded data and the second encoded data are then output as channel data written to the disk storage medium.

6574773, Jun 3, 2003

Mar 9, 2000

09/523922

Stephen A. Turk - Longmont CO 80501
Christopher P. Zook - Longmont CO 80503

H03M 746

714792, 341 59

A cost-effective high-throughput enumerative encoder is disclosed for encoding m-bit input datawords in an input data stream into n-bit output codewords in an encoded output data stream for use in a communication channel. The enumerative encoder comprises an input buffer for storing a plurality of bits in the input data stream, and a plurality of segmented compare tables for encoding the bits stored in the input buffer into the encoded output data stream, wherein each segmented compare table represents a segment of a full compare table of an enumerative trellis. A cost-effective high-throughput enumerative decoder is also disclosed for decoding n-bit input codewords in a received data stream into m-bit output datawords in a decoded data stream for use in a communication channel. The enumerative decoder comprises an input buffer for storing a plurality of bits in the received data stream, and a plurality of segmented compare tables for decoding the bits stored in the input buffer into the decoded data stream, wherein each segmented compare table represents a segment of a full compare table of an enumerative trellis.

6345074, Feb 5, 2002

Mar 20, 1998

09/045612

Stephen A. Turk - Longmont CO
David E. Reed - Westminster CO
Richard T. Behrens - Lafayette CO

Cirrus Logic, Inc. - Austin TX

H03D 100

375341, 370262, 360 53, 360 7708, 714794, 714795, 714796

A disc storage system servo code detector is disclosed that provides enhanced error correction capabilities during both tracking and seeking by increasing a minimum distance d between valid codewords and by increasing a minimum distance {circumflex over ( )}d from the signal space between adjacent codewords to the decision boundaries of all other valid codewords. The signal space with respect to the minimum distances is not a limiting aspect of the invention; however, in the preferred embodiment the codewords are selected to maximize the minimum distances in Euclidean space. Thus, the read signal is sampled and equalized according to a partial response spectrum, and maximum likelihood detection is employed to detect the servo codewords in Euclidean space. The code rate is selected according to certain design criteria such as the amount of error correction desired, the data density, and the cost and complexity of the encoder/decoder circuitry. After selecting the code rate and number of bits per codeword, a computer search is carried out to find a subset of codewords large enough to encode the track addresses while providing large minimum distance values for d and {circumflex over ( )}d.

6490110, Dec 3, 2002

Dec 19, 2000

09/740748

David E. Reed - Westminster CO
Stephen A. Turk - Longmont CO
Li Du - Broomfield CO

Cirrus Logic, Inc. - Austin TX

G11B 509

360 48, 360 53, 360 7708

Servo circuitry is disclosed that is configured to operate with a magnetic disk drive system. The servo circuitry is comprised of a first servo detector system, a second servo detector system, and a comparator. The first servo detector system and the second servo detector system each receive samples, taken from a read signal, that include servo data. The first servo detector system compares the samples to a plurality of servo codes to generate a first selected code. The second servo detector system compares a first shifted version of the samples to the plurality of servo codes to generate a second selected code. The comparator receives the selected codes and selects one of the selected codes. The selected code represents the servo data. The servo circuitry could also include a third servo detector system that operates on a second shifted version of the samples.

2002006, Jun 6, 2002

Dec 5, 2000

09/730091

David Reed - Westminster CO, US
Stephen Turk - Longmont CO, US
Li Du - Broomfield CO, US

Cirrus Logic, Inc.

G06F011/00

714/054000

Servo circuitry is disclosed that is configured to operate with a magnetic disk drive system. The servo circuitry is comprised of a first servo detector system, a second servo detector system, and a comparator. The first servo detector system and the second servo detector system each receive samples, taken from a read signal, that include servo data. The first servo detector system compares the samples to a plurality of servo codes to generate a first selected code. The second servo detector system compares a first shifted version of the samples to the plurality of servo codes to generate a second selected code. The comparator receives the selected codes and selects one of the selected codes. The selected code represents the servo data. The servo circuitry could also include a third servo detector system that operates on a second shifted version of the samples. Alternatively, the first servo detector system, the second servo detector system, and the third servo detector system could each be programmed with different servo codes. The first servo detector system compares the samples to a plurality of first servo codes. The second servo detector system compares the samples to a plurality of second servo codes. The third servo detector system compares the samples to a plurality of third servo codes. The second servo codes and the third servo codes are shifted versions of the first servo codes. In either embodiment, the servo circuitry advantageously has improved phase shift tolerance.

7262717, Aug 28, 2007

Mar 22, 2006

11/387093

John L. Melanson - Austin TX, US
Stephen Alan Turk - Longmont CO, US

Cirrus Logic, Inc. - Austin TX

H03M 7/00

341 61, 341 60

Digital filtering and sample rate conversion blocks are combined in order to reduce hardware and/or computational complexity. Input data samples provided at a first sample rate are converted to output data samples at a second sample rate unequal to the first sample rate. An Infinite Impulse Response filter having internal states are updated at the first sample rate filters the input data samples in, to produce filtered data samples at the first sample rate. Output data samples are output at the second sample rate, where each output data sample is created as the sum of at least two intermediate products, a first intermediate product and a second intermediate product. The first intermediate product is defined by a first function of the internal states multiplied by a first function of the time difference between output samples and internal state updates, and the second intermediate product is defined by a second function of the internal states multiplied by a second function of the time difference between output samples and internal state updates.

7242326, Jul 10, 2007

Dec 23, 2005

11/318271

John L. Melanson - Austin TX, US
Stephen Alan Turk - Longmont CO, US

Cirrus Logic, Inc. - Austin TX

H03M 7/00

341 61

Digital filtering and sample rate conversion blocks are combined in order to reduce hardware and/or computational complexity. A novel filter design is used to perform sample rate conversion. The filter may be combined with another digital filter. Two embodiment may be used to achieve this function. In a first embodiment, the filter may be clocked at a first (i. e. , input) data rate (i. e. , before rate conversion). In a second embodiment, the filter may be clocked at the second (i. e. , output) data rate (i. e. , after rate conversion). In both cases, the filter's basic structure remains essentially the same, but some extra terms are added to handle the rate conversion. The present application is directed toward a sample-rate conversion filter using the output data rate clock as the filter clock.

6271776, Aug 7, 2001

Nov 30, 1999

9/451392

Stephen Alan Turk - Longmont CO
Christopher Paul Zook - Longmont CO

Cirrus Logic, Inc. - Austin TX

H03M 700

341 95

An encoder/decoder (ENDEC) avoids undesired sequences in encoded data blocks, such as quasi-catastrophic sequences, by essentially skipping over inputs that create the undesired sequences. Upon recognizing that a particular incoming data block has a value corresponding to an undesired sequence, the ENDEC does not use the problematic value for the incoming data block, but rather adds an offset to the value for the incoming data block, and uses the offset value for producing an encoded output sequence for the data block.