STEPHANIE TRAN, CCC SLP
Speech Language Pathology at Bascom Ave, San Jose, CA
License number
California SP#24504
Category
Speech Language Pathology
Type
Speech-Language Pathologist
Address
Address
828 S Bascom Ave SUITE 100, San Jose, CA 95128
Phone
(408) 793-5959
Personal information
See more information about STEPHANIE TRAN at radaris.comName
Address
Phone
432 War Admiral Ave APT 3, San Jose, CA 95111
535 Penitencia St APT 3, Milpitas, CA 95035
56 Oakmont Dr, Daly City, CA 94015
41 Grandview St APT 1304, Santa Cruz, CA 95060
34 El Cencerro, Rancho Santa Margarita, CA 92688
Professional information
See more information about STEPHANIE TRAN at trustoria.com
Stephanie Tran - San Jose, CA
Stephanie Tran - San Jose, CA
Work:
Kaiser Foundation Rehabilitation Center
Speech & Language Pathology Intern Golden Gate Regional Center
Substitute Teacher Golden Gate Regional Center - San Francisco, CA
Personal Aide West Portal Elementary School, John Muir Elementary School - San Francisco, CA
Speech & Language Pathology Intern Jennifer Katz Inc - San Francisco, CA
Interpreter San Francisco State University - San Francisco, CA
Graduate Student Clinician, Adult Accent Modification Clinic Caesar Chavez School Clinic - San Francisco, CA
Graduate Student Clinician LEVANA Autism Support Services - San Francisco, CA
Respite Care Worker Autism Spectrum Disorders Child Clinic - San Francisco, CA
Graduate Student Clinician AAC Clinic Adult Conversation Club - San Francisco, CA
Undergraduate Clinic Aide AAC Clinic Adult Conversation Club - San Francisco, CA
Undergraduate Clinic Aide, Child Speech
Speech & Language Pathology Intern Golden Gate Regional Center
Substitute Teacher Golden Gate Regional Center - San Francisco, CA
Personal Aide West Portal Elementary School, John Muir Elementary School - San Francisco, CA
Speech & Language Pathology Intern Jennifer Katz Inc - San Francisco, CA
Interpreter San Francisco State University - San Francisco, CA
Graduate Student Clinician, Adult Accent Modification Clinic Caesar Chavez School Clinic - San Francisco, CA
Graduate Student Clinician LEVANA Autism Support Services - San Francisco, CA
Respite Care Worker Autism Spectrum Disorders Child Clinic - San Francisco, CA
Graduate Student Clinician AAC Clinic Adult Conversation Club - San Francisco, CA
Undergraduate Clinic Aide AAC Clinic Adult Conversation Club - San Francisco, CA
Undergraduate Clinic Aide, Child Speech
Education:
San Francisco State University
M.S. in Communicative Disorders San Francisco State University
B.A. in Communicative Disorders
M.S. in Communicative Disorders San Francisco State University
B.A. in Communicative Disorders
Programmable Series On-Chip Termination Impedance And Impedance Matching
Programmable Series On-Chip Termination Impedance And Impedance Matching
US Patent:
6836144, Dec 28, 2004
Filed:
Jul 26, 2002
Appl. No.:
10/206250
Inventors:
John Henry Bui - San Jose CA
John Costello - Los Altos CA
Stephanie Tran - San Jose CA
John Costello - Los Altos CA
Stephanie Tran - San Jose CA
Assignee:
Altera Corporation - San Jose CA
International Classification:
H03K 512
US Classification:
326 32, 326 30, 326 26, 326 27, 327108, 327170, 327112
Abstract:
Circuits may provide series on-chip termination impedance to one or more input/output pins. In one embodiment, two off-chip reference resistors in combination with internal calibration circuitry are used to control termination transistors coupled to several input/output (I/O) pins. The termination transistors behave as programmably adjustable termination resistors that match the impedance of external resistors. By using only a small number of reference resistors (e. g. , 2 resistors) for a large number of I/O pins, the present invention eliminates the external components that would otherwise be needed to provide resistance termination. The effective series termination resistance may be programmed, enabling the termination resistance to meet different I/O standards. Further, the resistance termination techniques of the present invention are not sensitive to process, voltage supply, and temperature (PVT) variations.
Charge Pump Circuits And Methods
Charge Pump Circuits And Methods
US Patent:
6774707, Aug 10, 2004
Filed:
Jan 14, 2002
Appl. No.:
10/050004
Inventors:
Mian Smith - Los Altos CA
Myron Wong - Fremont CA
Guu Lin - San Jose CA
Stephanie Tran - San Jose CA
Myron Wong - Fremont CA
Guu Lin - San Jose CA
Stephanie Tran - San Jose CA
Assignee:
Altera Corporation - San Jose CA
International Classification:
G05F 110
US Classification:
327536
Abstract:
Charge pump circuits and methods of the present invention step up an input voltage to provide an output voltage. The charge pump circuits have one or more stages. Each stage may include a capacitor and a transistor. Each stage adds an incremental voltage to an input voltage. The capacitors elevate the voltage at a terminal of the transistors in each stage in response to a clock signal to provide the incremental voltage. The output voltage is the sum of the input voltage and the incremental voltages provided by each stage. One or more of the stages of the charge pump circuit may have a depletion transistor. Depletion transistors may be field-effect transistors that have a lower threshold voltage as a result of an implant in the channel region of the device.
Apparatus And Method For Input/Output Module That Optimizes Frequency Performance In A Circuit
Apparatus And Method For Input/Output Module That Optimizes Frequency Performance In A Circuit
US Patent:
8138787, Mar 20, 2012
Filed:
Jul 13, 2008
Appl. No.:
12/172247
Inventors:
Guu Lin - San Jose CA, US
Yen-Fu Lin - San Jose CA, US
Stephanie T. Tran - San Jose CA, US
Pooyan Khoshkhoo - Santa Clara CA, US
Yen-Fu Lin - San Jose CA, US
Stephanie T. Tran - San Jose CA, US
Pooyan Khoshkhoo - Santa Clara CA, US
Assignee:
Altera Corporation - San Jose CA
International Classification:
G06F 7/38, H03K 19/173
US Classification:
326 37, 326 38, 326 47
Abstract:
A circuit can include a module having signal pads that are configurable to route signals between the circuit and at least one external device. The module can also have unused pads that are interleaved between the signal pads. A circuit can include a module having signal pads that are configurable to route varying signals between the circuit and at least one external device. The module can also have voltage pads that are configurable to route substantially constant voltages between at least one external device and the circuit. The signal pads can be interleaved between the voltage pads. A module with one or more of these features can achieve ideal performance in both wire bond and flip chip packages with the flexibility of setting a different input/output utilization percentage within the module.
Flexible Data Strobe Signal Bus Structure For Wirebond And Flip-Chip Packaging
Flexible Data Strobe Signal Bus Structure For Wirebond And Flip-Chip Packaging
US Patent:
8385142, Feb 26, 2013
Filed:
May 12, 2009
Appl. No.:
12/464783
Inventors:
Guu Lin - San Jose CA, US
Yen-Fu Lin - San Jose CA, US
Mark W. Fiester - Redwood City CA, US
Stephanie T. Tran - San Jose CA, US
Yen-Fu Lin - San Jose CA, US
Mark W. Fiester - Redwood City CA, US
Stephanie T. Tran - San Jose CA, US
Assignee:
Altera Corporation - San Jose CA
International Classification:
G11C 5/06
US Classification:
365193, 365 63
Abstract:
An integrated circuit with a flexible data strobe signal (DQS) bus structure is presented. The integrated circuit has a number of input/output (I/O) modules with a number of data pins to receive and transmit data. In addition, a subset of the I/O modules also have a data strobe pin. The input/output modules are connected to data strobe signal buses having a fixed configuration. The configuration of the fixed DQS bus groups a number of data pins with a corresponding data strobe pin and the grouping of data pin spans multiple I/O modules. The integrated circuit also has a flexible data bus connected to the I/O modules. Data pins of I/O modules of a second integrated circuit are mapped a subset of the data pins of corresponding I/O modules of the integrated circuit. The flexible data strobe signal bus enables selection of the subset of data pins in the integrated circuit.
Electrostatic Discharge Protection Circuit
Electrostatic Discharge Protection Circuit
US Patent:
7271989, Sep 18, 2007
Filed:
Jun 3, 2004
Appl. No.:
10/861604
Inventors:
Cheng-Hsiung Huang - Cupertino CA, US
Guu Lin - San Jose CA, US
Shih-Lin S. Lee - San Jose CA, US
Chih-Ching Shih - Pleasanton CA, US
Irfan Rahim - San Jose CA, US
Stephanie T. Tran - San Jose CA, US
Guu Lin - San Jose CA, US
Shih-Lin S. Lee - San Jose CA, US
Chih-Ching Shih - Pleasanton CA, US
Irfan Rahim - San Jose CA, US
Stephanie T. Tran - San Jose CA, US
Assignee:
Altera Corporation - San Jose CA
International Classification:
H02H 9/00
US Classification:
361 911, 361 56
Abstract:
Integrated circuits are provided that have sensitive circuitry such as programmable polysilicon fuses. Electrostatic discharge (ESD) protection circuitry is provided that prevents damage or undesired programming of the sensitive circuitry in the presence of an electrostatic discharge event. The electrostatic discharge protection circuitry may have a power ESD device that limits the voltage level across the sensitive circuitry to a maximum voltage and that draws current away from the sensitive circuitry when exposed to ESD signals. The electrostatic discharge protection circuitry may also have an ESD margin circuit that helps to prevent current flow through the sensitive circuitry when the maximum voltage is applied across the sensitive circuitry.
Electrostatic Discharge Protection Circuit
Electrostatic Discharge Protection Circuit
US Patent:
7400480, Jul 15, 2008
Filed:
Aug 7, 2007
Appl. No.:
11/890933
Inventors:
Cheng-Hsiung Huang - Cupertino CA, US
Guu Lin - San Jose CA, US
Shih-Lin S. Lee - San Jose CA, US
Chih-Ching Shih - Pleasanton CA, US
Irfan Rahim - San Jose CA, US
Stephanie T. Tran - San Jose CA, US
Guu Lin - San Jose CA, US
Shih-Lin S. Lee - San Jose CA, US
Chih-Ching Shih - Pleasanton CA, US
Irfan Rahim - San Jose CA, US
Stephanie T. Tran - San Jose CA, US
Assignee:
Altera Corporation - San Jose CA
International Classification:
H02H 3/22
US Classification:
361 56, 361111
Abstract:
Integrated circuits are provided that have sensitive circuitry such as programmable polysilicon fuses. Electrostatic discharge (ESD) protection circuitry is provided that prevents damage or undesired programming of the sensitive circuitry in the presence of an electrostatic discharge event. The electrostatic discharge protection circuitry may have a power ESD device that limits the voltage level across the sensitive circuitry to a maximum voltage and that draws current away from the sensitive circuitry when exposed to ESD signals. The electrostatic discharge protection circuitry may also have an ESD margin circuit that helps to prevent current flow through the sensitive circuitry when the maximum voltage is applied across the sensitive circuitry.
Signal Timing For I/O
Signal Timing For I/O
US Patent:
7317644, Jan 8, 2008
Filed:
Dec 15, 2005
Appl. No.:
11/303250
Inventors:
Guu Lin - San Jose CA, US
Stephanie T. Tran - San Jose CA, US
Yen-Fu Lin - San Jose CA, US
Stephanie T. Tran - San Jose CA, US
Yen-Fu Lin - San Jose CA, US
Assignee:
Altera Corporation - San Jose CA
International Classification:
G11C 7/00
US Classification:
365194, 36518902, 365233
Abstract:
Circuits, methods, and apparatus for ordering the timing of clock and data signals. Programmable delay cells are utilized in a data output cell to control a critical multiple data rate input/output write timing so the output can achieve better performance, such as higher maximum frequency of output (Fmax) performance. The delay cells ensure that critical timing criteria between clock signals and data high and low signals are satisfied so that there is a reduced chance of output glitching.
Flexible Macrocell Interconnect
Flexible Macrocell Interconnect
US Patent:
7573297, Aug 11, 2009
Filed:
Dec 11, 2006
Appl. No.:
11/609257
Inventors:
Guu Lin - San Jose CA, US
Stephanie Tran - San Jose CA, US
Bruce Pederson - San Jose CA, US
Brad Vest - San Jose CA, US
Jim Park - San Jose CA, US
Jay Schleicher - Santa Clara CA, US
Stephanie Tran - San Jose CA, US
Bruce Pederson - San Jose CA, US
Brad Vest - San Jose CA, US
Jim Park - San Jose CA, US
Jay Schleicher - Santa Clara CA, US
Assignee:
Altera Corporation - San Jose CA
International Classification:
H03K 19/177
US Classification:
326 41, 326 47
Abstract:
Methods and apparatus for novel routing structures and methods that improve fitting of user-defined functions onto programmable logic devices. In particular, second time fitting is improved. Exemplary structures and methods include allowing product terms to be expanded using inputs from more than one neighboring macrocell by providing multiple expansion and bypassing paths. Also, product term OR shifting prevents macrocell output stages from being buried and made inaccessible, and macrocell outputs are provided on expander word lines, increasing efficiency of those lines, as well as conserving routing resources. Expansion, bypassing, OR shifting, and expander word lines may terminate at logic array block boundaries or may continue beyond these boundaries to other logic array blocks.
Flexible Macrocell Interconnect
Flexible Macrocell Interconnect
US Patent:
6927601, Aug 9, 2005
Filed:
Nov 21, 2002
Appl. No.:
10/301506
Inventors:
Guu Lin - San Jose CA, US
Stephanie Tran - San Jose CA, US
Bruce Pederson - San Jose CA, US
Brad Vest - San Jose CA, US
Jim Park - San Jose CA, US
Jay Schleicher - Santa Clara CA, US
Stephanie Tran - San Jose CA, US
Bruce Pederson - San Jose CA, US
Brad Vest - San Jose CA, US
Jim Park - San Jose CA, US
Jay Schleicher - Santa Clara CA, US
Assignee:
Altera Corporation - San Jose CA
International Classification:
H03K019/177
US Classification:
326 41, 326 47
Abstract:
Methods and apparatus for novel routing structures and methods that improve fitting of user-defined functions onto programmable logic devices. In particular, second time fitting is improved. Exemplary structures and methods include allowing product terms to be expanded using inputs from more than one neighboring macrocell by providing multiple expansion and bypassing paths. Also, product term OR shifting prevents macrocell output stages from being buried and made inaccessible, and macrocell outputs are provided on expander word lines, increasing efficiency of those lines, as well as conserving routing resources. Expansion, bypassing, OR shifting, and expander word lines may terminate at logic array block boundaries or may continue beyond these boundaries to other logic array blocks.