SRIRAM NARAYAN
Pilots at Palmdale Ct, Pleasanton, CA

6856178, Feb 15, 2005

Jul 31, 2003

10/631285

Sriram Narayan - Pleasanton CA, US

Silicon Bridge, Inc. - Fremont CA

H03B001/00

327108, 327112, 326 87

A high-speed I/O driver includes circuitry that is configurable to meet single-ended and differential I/O signal standards. For one embodiment, the driver includes four input circuits that can be configured to implement two CMOS inverters to process single-ended signals or configured to implement a differential circuit to process differential signals.

2012007, Mar 22, 2012

Sep 17, 2010

12/884305

Peng Li - Palo Alto CA, US
Masashi Shimanouchi - San Jose CA, US
Weiqi Ding - Fremont CA, US
Sriram Narayan - Pleasanton CA, US
Daniel Tun Lai Chow - Foster City CA, US
Mingde Pan - Morgan Hill CA, US

G06F 11/00

714704, 714E11004

An integrated circuit (“IC”) may include circuitry for use in testing a serial data signal. The IC may include circuitry for transmitting the serial data signal with optional jitter, optional noise, and/or controllably variable drive strength. The IC may also include circuitry for receiving the serial data signal and performing a bit error rate (“BER”) analysis in such a signal. The IC may provide output signals indicative of results of its operations. The IC can operate in various modes to perform or at least emulate functions of an oscilloscope, a bit error rate tester, etc., for testing signals and circuitry with respect to jitter-tolerance, noise-tolerance, etc.

8228102, Jul 24, 2012

Mar 3, 2010

12/717062

Tien Duc Pham - San Jose CA, US
Richard G. Cliff - Los Altos CA, US
Tim Tri Hoang - San Jose CA, US
Weiqi Ding - Fremont CA, US
Sriram Narayan - Pleasanton CA, US
Thungoc M. Tran - San Jose CA, US
Kumara Tharmalingam - San Jose CA, US

Altera Corporation - San Jose CA

H03L 7/06

327156, 327141, 327147

One embodiment relates to an integrated circuit including a first strip of phase-locked loop (PLL) circuits on a first side of the integrated circuit, and a second strip of PLL circuits on a second side of the integrated circuit which is opposite from the first side. The PLL circuits in the first and second strips may be configured by programming the integrated circuit. Another embodiment relates to an integrated circuit including a plurality of phase-locked loop (PLL) circuits and a plurality of physical media attachment (PMA) triplet modules adjacent to the plurality of PLL circuits. Each PMA triplet module includes first, second and third channels. The first and third channels are arranged for use as receiving channels, and the second channel is arranged to be configurable as either a receiving channel or a clock multiplication unit. Other embodiments and features are also disclosed.

8335249, Dec 18, 2012

Nov 25, 2009

12/626379

Xiaoyan Su - San Jose CA, US
Sriram Narayan - Pleasanton CA, US
Wilson Wong - San Francisco CA, US

Altera Corporation - San Jose CA

H03H 7/40

375232

Equalizer circuitry on an integrated circuit (“IC”) includes first, second, and third continuous time, equalizer stages connected in series. Each stage includes peaking inductor circuitry. The equalizer circuitry may further include controllably variable, static, DC mode offset voltage compensation circuitry and/or dynamic, continuous mode, offset voltage compensation circuitry for respectively reducing DC voltage offset and/or time-varying, continuous mode voltage offset between an output of the third equalizer stage and utilization circuitry to which that output is applied. The first equalizer stage may be preceded by termination circuitry having controllably variable impedance. Differential circuitry and signalling may be used for various circuit components. The equalizer circuitry is particularly useful for fabrication as part of a programmable IC, using 28 nm CMOS technology, and as a receiver equalizer for a high-speed serial data signal having a bit rate of 20-25 Gbps.

2013011, May 9, 2013

Nov 4, 2011

13/289791

Weiqi DING - Fremont CA, US
Peng LI - Palo Alto CA, US
Sriram NARAYAN - Pleasanton CA, US

H03K 5/159

375230

One embodiment relates to a receiver circuit for a data link. The receiver circuit includes at least a first signal path, a second signal path, and a path selector circuit. The first signal path includes first equalization circuitry, and the second signal path includes second equalization circuitry. The path selector circuit is configured to select one signal path of the first and second signal paths. Other embodiments and features are also disclosed.

8230281, Jul 24, 2012

Apr 13, 2009

12/422916

Sriram Narayan - Pleasanton CA, US
Xiaoyan Su - San Jose CA, US
Wilson Wong - San Francisco CA, US

Altera Corporation - San Jose CA

G01R 31/3177, G01R 31/40

714727, 714733, 327 54

A test driver transmitter drives a test signal through a resistive termination circuit to a first pin to test components on a board during a boundary scan test operation. A test receiver receives the test signal through a second pin and a pass gate coupled to the second pin during the boundary scan test operation. A test signal is transmitted to the test receiver during loopback operation through a loopback circuit.

5581536, Dec 3, 1996

Jun 7, 1995

8/484431

Hans W. Klein - Pleasanton CA
Sriram Narayan - Pleasanton CA

IMP, Inc. - San Jose CA

G11B 700

369124

A circuit for detecting when peaks occur in an amplitude modulated electrical signal, and for measuring in real time the amplitudes of the detected peaks. The circuit delays the input signal a short time, and then notes when the input signal and its delayed version have the same amplitude, thereby to detect when a peak has occurred. The amplitude of the peak is then measured. This circuit and technique have particular advantages when used as part of a servo control system that positions a read/write head to accurately follow moving tracks of recorded data on magnetic tape, magnetic disks, optical disks, and the like.

8537886, Sep 17, 2013

Jul 5, 2012

13/541917

Xiaoyan Su - San Jose CA, US
Sriram Narayan - Pleasanton CA, US

Altera Corporation - San Jose CA

H03H 7/40

375233, 375350

Systems and methods are disclosed for employing an equalization technique that improves equalizer input sensitivity and which reduces power consumption. In particular, an equalization architecture is described that includes a continuous-time linear equalizer and a decision feedback equalizer, each with offset cancellation that enables the equalizer to be used at high data rates. In addition, the equalization structure has a power-saving mode for bypassing the decision feedback equalizer. These offset cancellation and power-saving features are enabled and controlled using programmable logic on a programmable device.

8183921, May 22, 2012

Nov 24, 2010

12/954090

Sriram Narayan - Pleasanton CA, US
Xiaoyan Su - San Jose CA, US

Altera Corporation - San Jose CA

H03F 3/45

330259, 330 9

One embodiment relates to a continuous-time circuit configured with an offset cancellation loop. The continuous-time circuit includes a multi-stage amplifier chain, including a first amplifier stage and a last amplifier stage, and an offset cancellation loop. The offset cancellation loop is configured to receive an output of the last amplifier stage and to provide an offset correction voltage signal to the first amplifier stage. The offset compensation loop may create one dominant pole and a single consequential parasitic pole so as to have greater stability and may advantageously achieve a second-order roll-off in response magnitude at higher frequencies. Other embodiments, aspects, and features are also disclosed.

5491681, Feb 13, 1996

Dec 13, 1993

8/166247

Hans W. Klein - Pleasanton CA
Sriram Narayan - Pleasanton CA

I M P, Inc. - San Jose CA

G11B 700

369124

A circuit for detecting when peaks occur in an amplitude modulated electrical signal, and for measuring in real time the amplitudes of the detected peaks. The circuit delays the input signal a short time, and then notes when the input signal and its delayed version have the same amplitude, thereby to detect when a peak has occurred. The amplitude of the peak is then measured. This circuit and technique have particular advantages when used as part of a servo control system that positions a read/write head to accurately follow moving tracks of recorded data on magnetic tape, magnetic disks, optical disks, and the like.