SHAWN SEARLES
Pilots at Twilight Mesa Dr, Austin, TX

7701263, Apr 20, 2010

Mar 31, 2008

12/059595

Anil Kumar - Austin TX, US
Shawn Searles - Austin TX, US

GLOBALFOUNDRIES Inc. - Grand Cayman

H03B 1/00

327108, 327543, 327112

An apparatus including a bias voltage generator and one or more cascode drivers. Each of the one or more cascode drivers may include a plurality of cascode transistors. The bias voltage generator may control the cascode bias voltages provided to the cascode transistors based on a plurality of programmable control bits received by the bias voltage generator. The received plurality of programmable control bits may include a first set of programmable control bits, which may be used to control the magnitude of the cascode bias voltages, and a second set of programmable control bits, which may be used to control the stability of the cascode bias voltages.

7961533, Jun 14, 2011

May 27, 2008

12/127059

Shawn Searles - Austin TX, US

Advanced Micro Devices, Inc. - Sunnyvale CA

G11C 7/00

365193, 365191, 365233, 365194

Methods and apparatus for aligning a clock signal and a set of strobe signals are disclosed. In one embodiment, a memory controller includes a clock generator configured to generate the clock signal, and a respective strobe signal generator configured to generate each strobe signal. The memory controller further includes a phase recovery engine configured to receive an error signal from a corresponding memory device, wherein the error signal conveys an error indication indicative of an alignment of the strobe signal relative to the clock signal for each of a plurality of cycles of the strobe signal. The phase recovery engine includes an accumulator configured to maintain an accumulation value that depends upon the error indications for the plurality of cycles of the strobe signal. The strobe signal generator is configured to control a delay associated with generation of the strobe signal depending upon the accumulation value.

7983362, Jul 19, 2011

Apr 10, 2008

12/100996

Shawn Searles - Austin TX, US
Grace Chuang - Austin TX, US
Christopher M. Kurker - Austin TX, US
Curtis M. Brody - Austin TX, US

GLOBALFOUNDRIES, Inc. - Grand Cayman

H04L 27/00

375326, 327 52, 327 89, 327 96, 327127, 327246, 330250, 330252, 375318, 713401

Receiver architectures and bias circuits for a data processor are provided. A receiver architecture includes a linear receiver having a first input node for a data (DQ) signal, a second input node for a reference voltage, and output nodes for a differential output signal. The linear receiver compares the DQ signal to the reference voltage, and generates the differential output signal in response to the comparison. A sense amplifier is coupled to the linear receiver. The sense amplifier has input nodes connected to the output nodes of the linear receiver, and an output node for a binary output signal having voltage characteristics compatible with the processor. The sense amplifier transforms the differential output signal into the binary output signal. The receiver architecture also includes a programming architecture coupled to the linear receiver to set operating characteristics of the linear receiver.

7765425, Jul 27, 2010

Mar 21, 2006

11/385329

Shawn Searles - Austin TX, US
Donald Walters - Austin TX, US
Ravinder Rachala - Austin TX, US
Scott C. Johnson - Round Rock TX, US

GlobalFoundries, Inc. - Grand Cayman

G06F 1/04

713503, 713401

A system and method for using variable delay adjusters located at various points across an integrated circuit to measure clock skew and jitter for clock signals of the integrated circuit. A delay controller of the integrated circuit may measure and compensate for clock skew detected between two clock signals by configuring variable delay adjusters located inline with the respective clock signals. Such a delay controller may also use the variable delay adjusters to correct duty cycle errors in a clock signal and may further utilize the variable delay adjusters to measure and characterize jitter detected on the clock signals.

8356155, Jan 15, 2013

Oct 22, 2010

12/910412

Shawn Searles - Austin TX, US
Nicholas T. Humphries - Austin TX, US
Brian W. Amick - Bedford MA, US
Richard W. Reeves - Westborough MA, US
Hanwoo Cho - Acton MA, US
Ronald L. Pettyjohn - Concord MA, US

Advanced Micro Devices, Inc. - Sunnyvale CA

G06F 12/00

711167, 711E12001

A physical memory interface (Phy) and method of operating is disclosed. The Phy interface includes command and status registers (CSRs) configured to receive a first power context and second power context. Selection circuitry is configured to switch between the first and second power contexts. A plurality of adjustable delay elements are provided, each having a delay time responsive to the selected power context. A first set of CSRs configured may store the first power context and a second set of CSRs configured may store the second power context. The Phy interface may also include a plurality of drivers each having a selectable drive strength responsive to the selected power context. The Phy interface may also include a plurality of receivers each having a selectable termination impedance responsive to the selected power context. Switching between power contexts may result in adjusting of the delay elements, drive strength and/or termination impedance of one or more drivers/receivers.

2010027, Oct 28, 2010

Jul 1, 2010

12/828880

Shawn Searles - Austin TX, US
Scott C. Johnson - Round Rock TX, US
Grace I. Chuang - Austin TX, US

G06F 1/26

713330, 713300, 713340

A method and apparatus for powering up an integrated circuit (IC). An IC includes a plurality of power domains each coupled to receive power from one of a plurality of power sources. Each power domain includes a power-sensing unit. A power-sensing unit in a first one of the plurality of power domains is coupled to receive a first power ok signal from an upstream power domain, and is configured to assert a second power ok signal to be provided to a second power domain. A power-sensing unit in the second power domain is coupled to detect the presence of voltage in the first power domain, and to receive the first power ok signal. When the power-sensing unit in the second power domain has both sensed the presence of power in the first power domain and received the second power ok signal, a third power ok signal is asserted.

2012028, Nov 8, 2012

May 6, 2011

13/102975

Oswin E. Housty - Austin TX, US
Harold H. Bautista - Austin TX, US
Shawn Searles - Austin TX, US

G06F 11/267, G06F 12/00

714718, 711155, 711E12001, 714E11162

Techniques and structures are disclosed in which memory training for DDR or other memory can be performed more rapidly. A memory controller is configured so that one or more memory parameters (e.g., timing delay) can be determined for one or more hardware elements such as delay locked loops (DLLs). Training may be performed without intermediation by (or reporting of results to) a system BIOS. Thus, training may be performed fully in hardware. Voltage training techniques are also disclosed.

7770037, Aug 3, 2010

Apr 20, 2006

11/408226

Shawn Searles - Austin TX, US
Scott C. Johnson - Austin TX, US
Grace I. Chuang - Austin TX, US

Advanced Micro Devices, Inc. - Sunnyvale CA

G06F 1/26, G06F 1/32

713300, 713320, 713330, 713340, 327143

A method and apparatus for powering up an integrated circuit (IC). An IC includes a plurality of power domains each coupled to receive power from one of a plurality of power sources. Each power domain includes a power-sensing unit. A power-sensing unit in a first one of the plurality of power domains is coupled to receive a first power ok signal from an upstream power domain, and is configured to assert a second power ok signal to be provided to a second power domain. A power-sensing unit in the second power domain is coupled to detect the presence of voltage in the first power domain, and to receive the first power ok signal. When the power-sensing unit in the second power domain has both sensed the presence of power in the first power domain and received the second power ok signal, a third power ok signal is asserted.

8542068, Sep 24, 2013

Dec 21, 2011

13/332990

Bruce A. Doyle - Longmont CO, US
Emerson S. Fang - Fremont CA, US
Alvin L. Loke - Fort Collins CO, US
Shawn Searles - Austin TX, US
Stephen F. Greenwood - Fort Collins CO, US

Advanced Micro Devices, Inc. - Sunnyvale CA

H03L 7/00

331 17, 331 57

A device may include an oscillator to generate a clock signal based on first and second control signals. The oscillator may include a first buffer stage a second buffer stage. The first buffer stage may output a first signal that is based on an output of the second buffer stage and the first control signal. The second buffer stage may output the clock signal. The clock signal may be based on the first signal and the second control signal.