Shailesh Shah
Engineers in San Jose, CA

6822899, Nov 23, 2004

Dec 23, 2002

10/328265

Khaled Boulos - Sunnyvale CA
Shailesh Shah - San Jose CA
Carlos Awong - San Francisco CA

Cypress Semiconductor Corporation - San Jose CA

G11C 1606

36518509, 36518502, 36518523

In the present invention a method and circuit are shown to protect flash memory from data corruption during a rapid power down. A circuit element detect the drop in power voltage and signals that any write operation being performed be switched into a programming phase, and at the same time increase the programming voltage to the flash memory to significantly reduce programming time. If the power drop occurs during an erase phase of a write operation, the erase operation is switched to a program operation using old data to program erased cells. If the power drop occurs during a programming phase of the write operation, the programming phase is continued but at a faster rate.

5835970, Nov 10, 1998

Dec 21, 1995

8/576505

Greg J. Landry - San Jose CA
Shailesh Shah - San Jose CA

Cypress Semiconductor Corp. - San Jose CA

G06F 1328

711218

An improved burst address generator that is coupled to a memory array receives as its inputs a N-bit start address and dynamically generates a burst sequence of 2. sup. N decoded addresses. The burst address generator is responsive to a mode-select signal that determines whether the burst address generator operates in a linear mode or a non-linear mode. A decoder is provided for decoding the start address. A wrap-around up-down 2. sup. N -bit shift register, coupled to the address decoder, receives the decoded start address from the address decoder and dynamically provides the proper burst address sequences in accordance to the selected mode. A start address storage element is also coupled to the shift register and the address decoder to keep track of the start address.

5490115, Feb 6, 1996

Jul 29, 1994

8/282314

Shailesh Shah - San Jose CA
Gregory J. Landry - Santa Clara CA

Cypress Semiconductor Corp. - San Jose CA

G11C 700

365201

A computer memory system incorporates a gang write circuit block to reduce the number of clock cycles required write a background pattern to memory cells during a memory test operation. The computer memory system includes (1) a two-dimensional array having multiple memory cells arranged in M rows and N columns and (2) the gang write circuit block for writing to N memory cells located in a row during one cycle and for writing to all of the memory cells in M cycles. The gang write circuit block may include two inverters for each column of the memory array and two test signals for the inverters. The background pattern may be all 1's, all 0's or some combination of 1's and 0's. The gang write circuit block becomes inactive during a normal read and write operation. When all the word lines of the computer memory system are selected, all the memory cells are written simultaneously.

5559465, Sep 24, 1996

Jul 29, 1994

8/283223

Shailesh Shah - San Jose CA

Cypress Semiconductor Corporation - San Jose CA

H03K 1704

327374

An output preconditioning circuit with an output level latch is provided to precondition the output to an intermediate level and to clamp the output to that level before the actual data from a memory cell arrives at the output. Since the actual data has to charge or discharge the output from some intermediate level rather than the maximum output swing level or the minimum output swing level, as in the normal case, this results in a reduced delay in charging or discharging the output. The output preconditioning circuit which may be coupled to a heavy load or a light load can eliminate oscillation of the output because of the output level latch. The preconditioning system includes (1) a level sense circuit for sensing a voltage level of the circuit output and comparing the voltage level to two different reference voltages and (2) a preconditioning circuit including a latch circuit for latching the values in response to the comparison and a driver-and-clamp circuit for clamping the circuit output to an intermediate voltage level when the values indicate that the circuit output is out of the desired range.

5652732, Jul 29, 1997

Dec 22, 1995

8/577716

Shailesh Shah - San Jose CA

Cypress Semiconductor Corp. - San Jose CA

G11C 800

365233

A memory device including a memory array and a series of sense amplifiers coupled to the memory array. The memory array includes numerous memory cells. A clock transmission line receives a clock signal and forms a clock word line within the memory device. A circuit is coupled to the clock transmission line and includes at least one transistor device coupled to the clock transmission line to receive the clock signal. The circuit also includes a clock output coupled to one of the sense amplifiers.

5933032, Aug 3, 1999

Jul 21, 1997

8/897375

Shailesh Shah - San Jose CA
Gregory J. Landry - San Jose CA

Cypress Semiconductor Corp. - San Jose CA

H03K 500

327 34

A circuit for generating a pulse signal in response to an input signal. The circuit provides a pulse width for the pulse signal. A first logic device receives the input signal and generates a first intermediate signal. A delay device is coupled to the first logic device and receives the first intermediate signal. The delay device generates a second intermediate signal in response to the first intermediate signal after a period of time. The second intermediate signal has the same state as the second intermediate signal. A second logic device is coupled to both the first logic device and the delay device. The second logic device generates the pulse signal in response to the first intermediate signal.

5835401, Nov 10, 1998

Dec 5, 1996

8/760823

Gary W. Green - Pleasanton CA
John Q. Torode - Hunts Point WA
T. J. Rodgers - Woodside CA
Shailesh Shah - San Jose CA

Cypress Semiconductor Corporation - San Jose CA

G11C 1124

365149

A method and circuit for hiding a refresh of DRAM cells in a memory device. One embodiment of the circuit includes a selection circuit configured to select a first row of DRAM cells in the memory circuit in response to an active control signal. As a result, data may be read from or written to at least one of the DRAM cells in the first row. The selection circuit is also configured to couple a refresh address to a second row of DRAM cells in the memory circuit in response to an inactive state control signal. The second row of cells is refreshed when the selection circuit accesses the second row. For one embodiment, the DRAM cells are four transistor DRAM cells.

6222393, Apr 24, 2001

Jul 20, 1999

9/357474

Shailesh Shah - San Jose CA
Gregory J. Landry - San Jose CA

Cypress Semiconductor Corporation - San Jose CA

H03K 500

327 34

A circuit for generating a pulse signal in response to an input signal. The circuit provides a pulse width for the pulse signal. A first logic device receives the input signal and generates a first intermediate signal. A delay device is coupled to the first logic device and receives the first intermediate signal. The delay device generates a second intermediate signal in response to the first intermediate signal after a period of time. The second intermediate signal has the same state as the second intermediate signal. A second logic device is coupled to both the first logic device and the delay device. The second logic device generates the pulse signal in response to the first intermediate signal.

7221200, May 22, 2007

Mar 8, 2005

11/075632

Prasad Kotra - Bangalore, IN
Sunil Thamaran - Bangalore, IN
Shailesh Shah - San Jose CA, US

Cypress Semiconductor Corp. - San Jose CA

H03L 7/00

327143, 327142

A programmable low voltage reset apparatus for a device having a plurality of power supplies comprises a low voltage signal generator for sensing when a power supply output decreases below a predetermined voltage and generating a reset signal, a reset selector for selecting one of the power supplies, and a programmable reference voltage for varying a reference voltage according to the voltage of the selected power supply.

7170179, Jan 30, 2007

Apr 29, 2002

10/134764

Shailesh Shah - San Jose CA, US

Cypress Semiconductor Corp. - San Jose CA

H01L 23/48, H01L 25/00

257773, 257786, 326 41

A chip generally comprising a logic circuit and a plurality of pads. The logic circuit may be configured to operate in a plurality of modes in response to a mode signal. The pads may be configurable into a plurality of subsets such that one of the subsets is used by the logic circuit at a time in response to the mode signal.