Sean Michael Mulholland
Engineers in Colorado Springs, CO

6493283, Dec 10, 2002

Nov 22, 2000

09/721324

Keith A. Ford - Colorado Springs CO
Iulian C. Gradinariu - Colorado Springs CO
Bogdan I. Georgescu - Colorado Springs CO
Sean B. Mulholland - Colorado Springs CO
John J. Silver - Monument CO
Danny L. Rose - Monument CO

Cypress Semiconductor Corp. - San Jose CA

G11C 800

36523003, 365 63, 36523005

A circuit comprising a plurality of groups of memory cells and a control circuit. The plurality of groups of memory cells may each (i) have a first and a second bitline and (ii) configured to read and write data to one or more of the plurality of groups of memory cells. The control circuit may be configured to select an active group of the plurality of groups in response to one or more control signals. The control circuit may be implemented within the groups of memory cells.

6662315, Dec 9, 2003

Nov 26, 2002

10/305699

Iulian C. Gradinariu - Colorado Springs CO
John J. Silver - Monument CO
Keith A. Ford - Colorado Springs CO
Sean B. Mulholland - Colorado Springs CO

Cypress Semiconductor Corporation - San Jose CA

G06F 1100

714 42

An asynchronous memory device includes parallel test circuitry configured to interface with a single-ended output data path of the memory device and, in some cases, to provide a measure of a slowest cell access time for the memory device. The parallel test circuitry may include first circuitry configured to receive logic signals from a plurality of cells of the memory device and to provide first output signals indicative of logic states of the plurality of cells; and second circuitry configured to receive the first output signals and to produce a second output signal indicative of the logic states of the first output signals therefrom. For example, the first circuitry and the second circuitry may be configured as a wired NAND and wired NOR combination. In some cases, one or more of the cells may be included within a redundant row or column of the memory device. The first circuitry may include one or more circuits, each including an input path from a first number of the plurality of cells and configured to provide at least one of the first output signals.

6629185, Sep 30, 2003

Dec 6, 1999

09/455272

John Silver - Monument CO
Iulian Gradinariu - Colorado Springs CO
Keith Ford - Colorado Springs CO
Sean Mulholland - Colorado Springs CO

Cypress Semiconductor Corp. - San Jose CA

G06F 1314

710307

An apparatus comprising a first bus, a second bus, a memory and one or more interconnections. The memory may be connected to the first bus and the second bus and may be configured to transfer data over the first bus and the second bus. The one or more interconnections may be connected between one or more data lines of the first bus and the second bus to control a bit-width of the first and second buses.

6674682, Jan 6, 2004

Jul 19, 2002

10/199560

Keith A. Ford - Colorado Springs CO
Iulian C. Gradinariu - Colorado Springs CO
Bogdan I. Georgescu - Colorado Springs CO
Sean B. Mulholland - Colorado Springs CO
John J. Silver - Monument CO
Danny L. Rose - Monument CO

Cypress Semiconductor Corp. - San Jose CA

G11C 800

36523003, 365226

A method for providing at least 2 Meg of SRAM cells having a maximum average operating current of approximately 9. 43 mA comprising the steps of (A) providing an address path configured to consume a maximum average operating current of approximately 2. 38 mA, (B) providing one or more sense amplifiers configured to consume a maximum average operating current of approximately 0. 91 mA, (C) providing one or more bitlines configured to consume a maximum average operating current of approximately 0. 94 mA and (D) providing a Q path configured to consume a maximum average operating current of approximately 0. 61 mA.

6005814, Dec 21, 1999

Apr 3, 1998

9/054654

Sean B. Mulholland - Colorado Springs CO
James D. Allan - Colorado Springs CO

Cypress Semiconductor Corporation - San Jose CA

G11C 700

365201

A robust system for entering a test mode in an integrated circuit, for example, a memory device, greatly eliminates the probability of unintentionally entering the test mode, yet provides a system of access through a precise address and control pin sequence. By using an existing control pin present on the integrated circuit as a clock signal input for a series of latches, the present scheme sets up a number of address with predetermined values in order to create a key that is correct only if all the addresses are at the correct values. The key, combined with the clock signal input, allows a test mode enable signal to pass through each latch in a series. By further requiring that the address sequence for the key be input during an otherwise "illegal" operation for the integrated circuit, the present scheme further ensures that unintentional entry to the test mode is avoided.

6163495, Dec 19, 2000

Sep 17, 1999

9/398735

Keith A. Ford - Colorado Springs CO
Iulian C. Gradinariu - Colorado Springs CO
Bogdan I. Georgescu - Colorado Springs CO
Sean B. Mulholland - Colorado Springs CO
John J. Silver - Monument CO
Danny L. Rose - Monument CO

Cypress Semiconductor Corp. - San Jose CA

G11C 800

36523003

A circuit comprising a first and second bitline, a plurality of groups of memory cells and a control circuit. The first and second bitlines may each be configured to read and write to one or more of the plurality of groups of memory cells. Each of the plurality of bitline pairs may be interdigitated. The control circuit may be configured to select an active group of said plurality of groups in response to one or more control signals. The control circuit may be implemented within the groups of memory cells.

6249464, Jun 19, 2001

Dec 15, 1999

9/461632

John J. Silver - Monument CO
Julian C. Gradinariu - Colorado Springs CO
Bogdan I. Georgescu - Colorado Springs CO
Keith A. Ford - Colorado Springs CO
Sean B. Mulholland - Colorado Springs CO
Danny L. Rose - Monument CO

Cypress Semiconductor Corp. - San Jose CA

G11C 700

365200

A circuit comprising a memory array and a logic circuit. The memory array may be configured to read or write data in response to (i) one or more enable signals and (ii) a global signal. The logic circuit may be configured to generate the enable signals in response to one or more address signals. De-assertion of the enable signals generally reduces current consumption in the memory array.