SCOTT HARRIS CRAVENS
Pilots at Trappers Pl, Fort Collins, CO

License number
Colorado A4034422
Issued Date
May 2015
Expiration Date
May 2017
Category
Airmen
Type
Authorized Aircraft Instructor
Address
Address
622 Trappers Pl, Fort Collins, CO 80550

Professional information

Scott Cravens Photo 1

Engineering Manager

Position:
R&D Manager at Avago Technologies
Location:
Fort Collins, Colorado Area
Industry:
Semiconductors
Work:
Avago Technologies since Mar 2008 - R&D Manager Intel Corporation Nov 2005 - Jul 2006 - Product Development Eng./Lab Manager Mary's Mountain Cookies Apr 2003 - Mar 2005 - Business Owner LSI Corporation Sep 1998 - Jan 2002 - Engineering Manager Symbios Logic Jun 1995 - Jun 1998 - Engineering Manager AT&T Jun 1993 - Jun 1995 - Manager of Application Engineering NCR Corp. Aug 1978 - Jun 1993 - Project Leader and Technical Manager
Education:
University of Pennsylvania - The Wharton School 1997 - 1997
Colorado State University 1981 - 1982
Oklahoma State University 1974 - 1978
BS, Electrical Engineering
Memorial High School 1972 - 1974
NA, Math/Science
Placer High School 1969 - 1971
NA
Interests:
Certificated Flight Instructor (Single Engine Land), Instrument Rated Commercial Pilot, Bible study and teaching, Snowboarding, Mountain Biking, SCUBA Diving
Honor & Awards:
• U.S. Patent No. 4,753,901, “Two Mask Planarization Technique for Planarized Trench Oxide Isolation of Integrated Devices”, Issued Jun. 1988 • Meritorious Technical Achievement Award, NCR Corp., 1993 • Member Technical Program Committee, Custom Integrated Circuits Conference, 1990 - 1996


Scott Cravens Photo 2

Two Mask Technique For Planarized Trench Oxide Isolation Of Integrated Devices

US Patent:
4753901, Jun 28, 1988
Filed:
Nov 15, 1985
Appl. No.:
6/798511
Inventors:
Daniel L. Ellsworth - Fort Collins CO
Scott H. Cravens - Fort Collins CO
Maurice M. Moll - Fort Collins CO
Assignee:
NCR Corporation - Dayton OH
International Classification:
H01L 21467, H01L 2176
US Classification:
437 67
Abstract:
A two mask process for forming dielectrically filled planarized trenches of arbitrary width in a semiconductor substrate, the masks being of such character that they are amenable to computerized generation. The first mask defines the active regions and subdivides the trench isolation regions into a succession of trench and plateau regions, where the widths of the trench and plateau regions fall within in a dimensional range constrained by photolithographic precision of the masks and the ability to conformally deposit dielectric material into the trenches. With the first etch mask in place, the semiconductor is anisotropically etched to formed the first trench regions. A conformal deposition of dielectric follows, and by virtue of the dimensional constraints ensures substantially void free trench dielectric and a concluding substantially planar topology of the dielectric on the substrate surface. Following the etch of the deposited dielectric to the level of the plateau and active region surfaces, a second mask, defined to be slightly larger than the active regions, is formed over the substrate. A selective etch is then applied to remove the plateau regions and thereby form new trenches approximating in depth the first trenches.